2 * Copyright (C) 2013 Samsung Electronics
4 * Configuration settings for the SAMSUNG EXYNOS5 board.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __CONFIG_EXYNOS5_COMMON_H
10 #define __CONFIG_EXYNOS5_COMMON_H
12 #define CONFIG_EXYNOS5 /* Exynos5 Family */
14 #include "exynos-common.h"
16 #define CONFIG_EXYNOS_SPL
20 #define CONFIG_CMD_TRACE
21 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
22 #define CONFIG_TRACE_EARLY_SIZE (8 << 20)
23 #define CONFIG_TRACE_EARLY
24 #define CONFIG_TRACE_EARLY_ADDR 0x50000000
27 /* Enable ACE acceleration for SHA1 and SHA256 */
28 #define CONFIG_EXYNOS_ACE_SHA
30 /* Power Down Modes */
31 #define S5P_CHECK_SLEEP 0x00000BAD
32 #define S5P_CHECK_DIDLE 0xBAD00000
33 #define S5P_CHECK_LPA 0xABAD0000
35 /* Offset for inform registers */
36 #define INFORM0_OFFSET 0x800
37 #define INFORM1_OFFSET 0x804
38 #define INFORM2_OFFSET 0x808
39 #define INFORM3_OFFSET 0x80c
41 /* select serial console configuration */
42 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
44 #define CONFIG_CMD_HASH
46 /* Thermal Management Unit */
47 #define CONFIG_EXYNOS_TMU
48 #define CONFIG_CMD_DTT
49 #define CONFIG_TMU_CMD_DTT
52 #define COPY_BL2_FNPTR_ADDR 0x02020030
53 #define CONFIG_SUPPORT_EMMC_BOOT
55 /* specific .lds file */
56 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
58 /* Boot Argument Buffer Size */
59 /* memtest works on */
60 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
61 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
62 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
66 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
67 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
68 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
69 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
70 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
71 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
72 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
73 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
74 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
75 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
76 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
77 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
78 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
79 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
80 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
81 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
83 #define CONFIG_SYS_MONITOR_BASE 0x00000000
85 #define CONFIG_SYS_MMC_ENV_DEV 0
87 #define CONFIG_SECURE_BL1_ONLY
89 /* Secure FW size configuration */
90 #ifdef CONFIG_SECURE_BL1_ONLY
91 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
93 #define CONFIG_SEC_FW_SIZE 0
96 /* Configuration of BL1, BL2, ENV Blocks on mmc */
97 #define CONFIG_RES_BLOCK_SIZE (512)
98 #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
99 #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
100 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
102 #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
103 #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
105 /* U-Boot copy size from boot Media to DRAM.*/
106 #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
107 #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
109 #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
110 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
113 #define CONFIG_SYS_I2C_S3C24X0
114 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
115 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
118 #ifdef CONFIG_SPI_FLASH
119 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
120 #define CONFIG_SF_DEFAULT_SPEED 50000000
123 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
124 #define CONFIG_ENV_SPI_MODE SPI_MODE_0
125 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
126 #define CONFIG_ENV_SPI_BUS 1
127 #define CONFIG_ENV_SPI_MAX_HZ 50000000
130 /* Ethernet Controllor Driver */
131 #ifdef CONFIG_CMD_NET
132 #define CONFIG_SMC911X
133 #define CONFIG_SMC911X_BASE 0x5000000
134 #define CONFIG_SMC911X_16_BIT
135 #define CONFIG_ENV_SROM_BANK 1
136 #endif /*CONFIG_CMD_NET*/
139 #define CONFIG_CMD_HASH
140 #define CONFIG_HASH_VERIFY
142 /* Enable Time Command */
145 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
146 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
148 #define CONFIG_USB_HOST_ETHER
149 #define CONFIG_USB_ETHER_ASIX
150 #define CONFIG_USB_ETHER_SMSC95XX
151 #define CONFIG_USB_ETHER_RTL8152
154 #define CONFIG_USB_BOOTING
155 #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
156 #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
157 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
159 #define BOOT_TARGET_DEVICES(func) \
165 #include <config_distro_bootcmd.h>
167 #ifndef MEM_LAYOUT_ENV_SETTINGS
168 /* 2GB RAM, bootm size of 256M, load scripts after that */
169 #define MEM_LAYOUT_ENV_SETTINGS \
170 "bootm_size=0x10000000\0" \
171 "kernel_addr_r=0x42000000\0" \
172 "fdt_addr_r=0x43000000\0" \
173 "ramdisk_addr_r=0x43300000\0" \
174 "scriptaddr=0x50000000\0" \
175 "pxefile_addr_r=0x51000000\0"
178 #ifndef EXYNOS_DEVICE_SETTINGS
179 #define EXYNOS_DEVICE_SETTINGS \
185 #ifndef EXYNOS_FDTFILE_SETTING
186 #define EXYNOS_FDTFILE_SETTING
189 #define CONFIG_EXTRA_ENV_SETTINGS \
190 EXYNOS_DEVICE_SETTINGS \
191 EXYNOS_FDTFILE_SETTING \
192 MEM_LAYOUT_ENV_SETTINGS \
195 #endif /* __CONFIG_EXYNOS5_COMMON_H */