2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
5 * U-Boot configuration for Embedded Planet EP8248 boards.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #define CONFIG_MPC8248
30 #define CPU_ID_STR "MPC8248"
32 #define CONFIG_EP8248 /* Embedded Planet EP8248 board */
36 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
38 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
39 #define CONFIG_ENV_OVERWRITE
42 * Select serial console configuration
44 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
48 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
49 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
50 #undef CONFIG_CONS_NONE /* It's not on external UART */
51 #define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
53 #define CFG_BCSR 0xFA000000
56 * Select ethernet configuration
58 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
59 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
62 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
63 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
66 #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
67 #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
68 #undef CONFIG_ETHER_NONE /* No external Ethernet */
70 #ifdef CONFIG_ETHER_ON_FCC
72 #define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
74 #if (CONFIG_ETHER_INDEX == 1)
76 /* - Rx clock is CLK10
78 * - BDs/buffers on 60x bus
81 #define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
82 #define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
83 #define CFG_CPMFCR_RAMTYPE 0
84 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
86 #elif (CONFIG_ETHER_INDEX == 2)
88 /* - Rx clock is CLK13
90 * - BDs/buffers on 60x bus
93 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
94 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
95 #define CFG_CPMFCR_RAMTYPE 0
96 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
98 #endif /* CONFIG_ETHER_INDEX */
100 #define CONFIG_MII /* MII PHY management */
101 #define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
103 * GPIO pins used for bit-banged MII communications
105 #define MDIO_PORT 0 /* Not used - implemented in BCSR */
106 #define MDIO_ACTIVE (*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
107 #define MDIO_TRISTATE (*(vu_char *)(CFG_BCSR + 8) |= 0x04)
108 #define MDIO_READ (*(vu_char *)(CFG_BCSR + 8) & 1)
110 #define MDIO(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
111 else *(vu_char *)(CFG_BCSR + 8) &= 0xFE
113 #define MDC(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
114 else *(vu_char *)(CFG_BCSR + 8) &= 0xFD
116 #define MIIDELAY udelay(1)
118 #endif /* CONFIG_ETHER_ON_FCC */
120 #ifndef CONFIG_8260_CLKIN
121 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
124 #define CONFIG_BAUDRATE 38400
130 #define CONFIG_BOOTP_BOOTFILESIZE
131 #define CONFIG_BOOTP_BOOTPATH
132 #define CONFIG_BOOTP_GATEWAY
133 #define CONFIG_BOOTP_HOSTNAME
137 * Command line configuration.
139 #include <config_cmd_default.h>
141 #define CONFIG_CMD_DHCP
142 #define CONFIG_CMD_ECHO
143 #define CONFIG_CMD_I2C
144 #define CONFIG_CMD_IMMAP
145 #define CONFIG_CMD_MII
146 #define CONFIG_CMD_PING
149 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
150 #define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
151 #define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
153 #if defined(CONFIG_CMD_KGDB)
154 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
155 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
156 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
157 #define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
158 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
161 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
162 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
165 * Miscellaneous configurable options
167 #define CFG_HUSH_PARSER
168 #define CFG_PROMPT_HUSH_PS2 "> "
169 #define CFG_LONGHELP /* undef to save memory */
170 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
171 #if defined(CONFIG_CMD_KGDB)
172 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
174 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
176 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
177 #define CFG_MAXARGS 16 /* max number of command args */
178 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
180 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
181 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
183 #define CFG_LOAD_ADDR 0x100000 /* default load address */
185 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
187 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
189 #define CFG_FLASH_BASE 0xFF800000
190 #define CFG_FLASH_CFI
191 #define CFG_FLASH_CFI_DRIVER
192 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
193 #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
195 #define CFG_DIRECT_FLASH_TFTP
197 #if defined(CONFIG_CMD_JFFS2)
198 #define CFG_JFFS2_FIRST_BANK 0
199 #define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
200 #define CFG_JFFS2_FIRST_SECTOR 0
201 #define CFG_JFFS2_LAST_SECTOR 62
202 #define CFG_JFFS2_SORT_FRAGMENTS
203 #define CFG_JFFS_CUSTOM_PART
206 #if defined(CONFIG_CMD_I2C)
207 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
208 #define CFG_I2C_SPEED 100000 /* I2C speed */
209 #define CFG_I2C_SLAVE 0x7F /* I2C slave address */
212 #define CFG_MONITOR_BASE TEXT_BASE
213 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
217 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
219 #define CFG_ENV_IS_IN_FLASH
221 #ifdef CFG_ENV_IS_IN_FLASH
222 #define CFG_ENV_SECT_SIZE 0x20000
223 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
224 #endif /* CFG_ENV_IS_IN_FLASH */
226 #define CFG_DEFAULT_IMMR 0x00010000
228 #define CFG_IMMR 0xF0000000
230 #define CFG_INIT_RAM_ADDR CFG_IMMR
231 #define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
232 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
233 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
234 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
236 /* Hard reset configuration word */
237 #define CFG_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
239 #define CFG_HRCW_SLAVE1 0
240 #define CFG_HRCW_SLAVE2 0
241 #define CFG_HRCW_SLAVE3 0
242 #define CFG_HRCW_SLAVE4 0
243 #define CFG_HRCW_SLAVE5 0
244 #define CFG_HRCW_SLAVE6 0
245 #define CFG_HRCW_SLAVE7 0
247 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
248 #define BOOTFLAG_WARM 0x02 /* Software reboot */
250 #define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
251 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
253 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
254 #if defined(CONFIG_CMD_KGDB)
255 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
258 #define CFG_HID0_INIT 0
259 #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
263 #define CFG_SIUMCR 0x01240200
264 #define CFG_SYPCR 0xFFFF0683
265 #define CFG_BCR 0x00000000
266 #define CFG_SCCR SCCR_DFBRG01
268 #define CFG_RMR RMR_CSRE
269 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
270 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
273 #define CFG_MPTPR 0x1300
274 #define CFG_PSDMR 0x82672522
275 #define CFG_PSRT 0x4B
277 #define CFG_SDRAM_BASE 0x00000000
278 #define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00001841)
279 #define CFG_SDRAM_OR 0xFF0030C0
281 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801)
282 #define CFG_OR0_PRELIM 0xFF8008C2
283 #define CFG_BR2_PRELIM (CFG_BCSR | 0x00000801)
284 #define CFG_OR2_PRELIM 0xFFF00864
286 #define CFG_RESET_ADDRESS 0xC0000000
288 #endif /* __CONFIG_H */