3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
8 * Based on davinci_dvevm.h. Original Copyrights follow:
10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33 #define CONFIG_DRIVER_TI_EMAC
34 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7
35 #define CONFIG_USE_NAND
40 #define CONFIG_ARM926EJS /* arm926ejs CPU core */
41 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
42 #define CONFIG_SOC_DA850 /* TI DA850 SoC */
43 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
44 #define CONFIG_SYS_OSCIN_FREQ 24000000
45 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
46 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
47 #define CONFIG_SYS_HZ 1000
48 #define CONFIG_SKIP_LOWLEVEL_INIT
49 #define CONFIG_DA850_LOWLEVEL
50 #define CONFIG_ARCH_CPU_INIT
51 #define CONFIG_DA8XX_GPIO
52 #define CONFIG_HOSTNAME enbw_cmc
53 #define CONFIG_DISPLAY_CPUINFO
55 #define MACH_TYPE_ENBW_CMC 3585
56 #define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC
61 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
62 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
63 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
64 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
66 /* memtest start addr */
67 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
69 /* memtest will be run on 16MB */
70 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
72 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
73 #define CONFIG_STACKSIZE (256*1024) /* regular stack */
78 #define CONFIG_SYS_NS16550
79 #define CONFIG_SYS_NS16550_SERIAL
80 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
81 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
82 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
83 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
84 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
85 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
86 #define CONFIG_SYS_DA850_LPSC_UART DAVINCI_LPSC_UART2
90 #define CONFIG_HARD_I2C
91 #define CONFIG_DRIVER_DAVINCI_I2C
92 #define CONFIG_SYS_I2C_SPEED 80000
93 #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
94 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
95 #define CONFIG_CMD_I2C
97 #define CONFIG_CMD_DTT
98 #define CONFIG_DTT_LM75
99 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
100 #define CONFIG_SYS_DTT_MAX_TEMP 70
101 #define CONFIG_SYS_DTT_LOW_TEMP -30
102 #define CONFIG_SYS_DTT_HYSTERESIS 3
105 * Flash & Environment
107 #ifdef CONFIG_USE_NAND
108 #define CONFIG_NAND_DAVINCI
109 #define CONFIG_SYS_NAND_USE_FLASH_BBT
110 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
111 #define CONFIG_SYS_NAND_PAGE_2K
112 #define CONFIG_SYS_NAND_CS 3
113 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
114 #define CONFIG_SYS_CLE_MASK 0x10
115 #define CONFIG_SYS_ALE_MASK 0x8
116 #undef CONFIG_SYS_NAND_HW_ECC
117 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
119 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=davinci_nand.1"
120 #define MTDPARTS_DEFAULT \
134 #define CONFIG_CMD_MTDPARTS
139 * Network & Ethernet Configuration
141 #ifdef CONFIG_DRIVER_TI_EMAC
143 #define CONFIG_BOOTP_DEFAULT
144 #define CONFIG_BOOTP_DNS
145 #define CONFIG_BOOTP_DNS2
146 #define CONFIG_BOOTP_SEND_HOSTNAME
147 #define CONFIG_NET_RETRY_COUNT 10
148 #define CONFIG_NET_MULTI
152 * Flash configuration
154 #define CONFIG_SYS_FLASH_CFI
155 #define CONFIG_FLASH_CFI_DRIVER
156 #define CONFIG_FLASH_CFI_MTD
157 #define CONFIG_SYS_FLASH_BASE 0x60000000
158 #define CONFIG_SYS_FLASH_SIZE 0x01000000
159 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
160 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
161 #define CONFIG_SYS_MAX_FLASH_SECT 128
162 #define CONFIG_FLASH_16BIT /* Flash is 16-bit */
164 #define CONFIG_CMD_FLASH
166 #define CONFIG_ENV_IS_IN_FLASH
167 #define CONFIG_SYS_MONITOR_LEN 0x80000
168 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
169 CONFIG_SYS_MONITOR_LEN)
170 #define CONFIG_ENV_SECT_SIZE (64 << 10)
171 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
172 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
173 CONFIG_ENV_SECT_SIZE)
174 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
175 #undef CONFIG_ENV_IS_IN_NAND
176 #define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \
177 CONFIG_ENV_SECT_SIZE)
179 #define xstr(s) str(s)
182 #define CONFIG_EXTRA_ENV_SETTINGS \
183 "u-boot_addr_r=c0000000\0" \
184 "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
185 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
186 "update=protect off " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
187 "erase " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
188 "cp.b ${u-boot_addr_r} " xstr(CONFIG_SYS_FLASH_BASE) \
190 "protect on " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
192 "rootpath=/opt/eldk-arm/arm\0" \
193 "nfsargs=setenv bootargs root=/dev/nfs rw " \
194 "nfsroot=${serverip}:${rootpath}\0" \
195 "ramargs=setenv bootargs root=/dev/ram rw\0" \
196 "addip=setenv bootargs ${bootargs} " \
197 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
198 ":${hostname}:${netdev}:off panic=1\0" \
199 "kernel_addr_r=c0700000\0" \
200 "fdt_addr_r=c0600000\0" \
201 "ramdisk_addr_r=c0b00000\0" \
202 "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \
203 xstr(CONFIG_HOSTNAME) ".dtb\0" \
204 "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
205 "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0" \
206 "nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0" \
207 "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0" \
208 "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \
209 "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
210 "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0" \
211 "addcon=setenv bootargs ${bootargs} console=ttyS2," \
213 "net_nfs=run load_fdt load_kernel; " \
214 "run nfsargs addip addcon addmtd addmisc;" \
215 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
216 "nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\
217 "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
218 "bootcmd=run net_nfs\0" \
220 "key_cmd_0=echo key: 0\0" \
221 "key_cmd_1=echo key: 1\0" \
222 "key_cmd_2=echo key: 2\0" \
223 "key_cmd_3=echo key: 3\0" \
228 "magic_keys=0123\0" \
229 "hwconfig=switch:lan=on,pwl=off\0" \
230 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
231 "addmisc=setenv bootargs ${bootargs} davinci_mmc.use_dma=0\0" \
232 "mtdids=" MTDIDS_DEFAULT "\0" \
233 "mtdparts=" MTDPARTS_DEFAULT "\0" \
238 * U-Boot general configuration
240 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
241 #define CONFIG_SYS_PROMPT "=> " /* Command Prompt */
242 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
243 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
244 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
245 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
246 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
247 #define CONFIG_VERSION_VARIABLE
248 #define CONFIG_AUTO_COMPLETE
249 #define CONFIG_SYS_HUSH_PARSER
250 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
251 #define CONFIG_CMDLINE_EDITING
252 #define CONFIG_SYS_LONGHELP
253 #define CONFIG_CRC32_VERIFY
254 #define CONFIG_MX_CYCLIC
255 #define CONFIG_BOOTDELAY 3
256 #define CONFIG_HWCONFIG
257 #define CONFIG_SHOW_BOOT_PROGRESS
258 #define CONFIG_BOARD_LATE_INIT
263 #include <config_cmd_default.h>
264 #define CONFIG_CMD_ENV
265 #define CONFIG_CMD_ASKENV
266 #define CONFIG_CMD_DHCP
267 #define CONFIG_CMD_DIAG
268 #define CONFIG_CMD_MII
269 #define CONFIG_CMD_PING
270 #define CONFIG_CMD_SAVES
271 #define CONFIG_CMD_MEMORY
272 #define CONFIG_CMD_CACHE
274 #ifndef CONFIG_DRIVER_TI_EMAC
275 #undef CONFIG_CMD_NET
276 #undef CONFIG_CMD_DHCP
277 #undef CONFIG_CMD_MII
278 #undef CONFIG_CMD_PING
281 #ifdef CONFIG_USE_NAND
282 #undef CONFIG_CMD_IMLS
283 #define CONFIG_CMD_NAND
285 #define CONFIG_CMD_MTDPARTS
286 #define CONFIG_MTD_DEVICE
287 #define CONFIG_MTD_PARTITIONS
289 #define CONFIG_RBTREE
290 #define CONFIG_CMD_UBI
291 #define CONFIG_CMD_UBIFS
294 #if !defined(CONFIG_USE_NAND) && \
295 !defined(CONFIG_USE_NOR) && \
296 !defined(CONFIG_USE_SPIFLASH)
297 #define CONFIG_ENV_IS_NOWHERE
298 #define CONFIG_SYS_NO_FLASH
299 #define CONFIG_ENV_SIZE (16 << 10)
300 #undef CONFIG_CMD_IMLS
301 #undef CONFIG_CMD_ENV
304 #define CONFIG_SYS_TEXT_BASE 0x60000000
305 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
306 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
307 #define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
309 #define CONFIG_VERSION_VARIABLE
310 #define CONFIG_ENV_OVERWRITE
312 #define CONFIG_PREBOOT "echo;" \
313 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
315 #define CONFIG_MISC_INIT_R
317 #define CONFIG_CMC_RESET_PIN 0x04000000
318 #define CONFIG_CMC_RESET_TIMEOUT 3
320 #define CONFIG_HW_WATCHDOG
321 #define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
322 #define CONFIG_SYS_WDT_PERIOD_LOW 0x0c000000
323 #define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
325 #define CONFIG_CMD_DATE
326 #define CONFIG_RTC_DAVINCI
330 #define CONFIG_GENERIC_MMC
331 #define CONFIG_DAVINCI_MMC
332 #define CONFIG_MMC_MBLOCK
333 #define CONFIG_DOS_PARTITION
334 #define CONFIG_CMD_FAT
335 #define CONFIG_CMD_MMC
339 #define CONFIG_OF_LIBFDT
343 #define CONFIG_SYS_DV_CLKMODE 0
344 #define CONFIG_SYS_DA850_PLL0_POSTDIV 0
345 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
346 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
347 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 /* 150MHz */
348 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
349 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
350 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
351 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
353 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1
354 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
355 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
356 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
358 #define CONFIG_SYS_DA850_PLL0_PLLM 18 /* PLL0 -> 456 MHz */
359 #define CONFIG_SYS_DA850_PLL1_PLLM 24 /* PLL1 -> 300 MHz */
362 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
363 DV_DDR_PHY_EXT_STRBEN | \
364 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
366 #define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \
367 (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
368 (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
369 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
370 (0x1 << DV_DDR_SDCR_DDREN_SHIFT) | \
371 (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
372 (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) | \
373 (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
374 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
375 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
376 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
378 #define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */
381 * freq = 150MHz -> t = 7ns
383 #define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \
384 (0x0d << DV_DDR_SDTMR1_RFC_SHIFT) | \
385 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
386 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
387 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
388 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
389 (7 << DV_DDR_SDTMR1_RC_SHIFT) | \
390 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
391 (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) | /* Reserved */ \
392 ((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT))
395 * freq = 150MHz -> t=7ns
397 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \
398 (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
399 (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
400 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
401 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
402 (15 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
403 (27 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
404 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
405 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
407 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000407
408 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
409 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
410 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
411 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
412 DAVINCI_SYSCFG_SUSPSRC_EMAC |\
413 DAVINCI_SYSCFG_SUSPSRC_I2C)
415 #define CONFIG_SYS_DA850_CS2CFG (DAVINCI_ABCR_WSETUP(2) | \
416 DAVINCI_ABCR_WSTROBE(6) | \
417 DAVINCI_ABCR_WHOLD(1) | \
418 DAVINCI_ABCR_RSETUP(2) | \
419 DAVINCI_ABCR_RSTROBE(6) | \
420 DAVINCI_ABCR_RHOLD(1) | \
421 DAVINCI_ABCR_ASIZE_16BIT)
423 #define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
424 DAVINCI_ABCR_WSTROBE(2) | \
425 DAVINCI_ABCR_WHOLD(1) | \
426 DAVINCI_ABCR_RSETUP(1) | \
427 DAVINCI_ABCR_RSTROBE(6) | \
428 DAVINCI_ABCR_RHOLD(1) | \
429 DAVINCI_ABCR_ASIZE_8BIT)
432 * NOR Bootconfiguration word:
434 * EMIFA access mode: 16 Bit
436 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
438 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY)
439 #define CONFIG_SYS_POST_WORD_ADDR 0x8001FFF0
440 #define CONFIG_LOGBUFFER
441 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
443 #define CONFIG_BOOTCOUNT_LIMIT
444 #define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE
446 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc0080000
447 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x60004000
448 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x70000
449 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
450 #endif /* __CONFIG_H */