ARMV7: AM3517/05: Add support for CraneBoard.
[oweals/u-boot.git] / include / configs / eb_cpux9k2.h
1 /*
2  * (C) Copyright 2008-2009
3  * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
4  * Jens Scharsig <esw@bus-elektronik.de>
5  *
6  * Configuation settings for the EB+CPUx9K2 board.
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26
27 #ifndef _CONFIG_EB_CPUx9K2_H_
28 #define _CONFIG_EB_CPUx9K2_H_
29
30 /*--------------------------------------------------------------------------*/
31
32 #define CONFIG_ARM920T          1       /* This is an ARM920T Core      */
33 #define CONFIG_AT91RM9200       1       /* It's an Atmel AT91RM9200 SoC */
34 #define CONFIG_EB_CPUX9K2       1       /* on an EP+CPUX9K2 Board       */
35 #define USE_920T_MMU            1
36
37 #define CONFIG_VERSION_VARIABLE 1
38 #define CONFIG_IDENT_STRING     " on EB+CPUx9K2"
39
40 #include <asm/arch/hardware.h>  /* needed for port definitions */
41
42 #define CONFIG_MISC_INIT_R
43
44 /*--------------------------------------------------------------------------*/
45 #define CONFIG_SYS_TEXT_BASE            0x00000000
46 #define CONFIG_SYS_LOAD_ADDR            0x21000000  /* default load address */
47
48 #define CONFIG_SYS_BOOT_SIZE            0x00 /* 0 KBytes */
49 #define CONFIG_SYS_U_BOOT_BASE          PHYS_FLASH_1
50 #define CONFIG_SYS_U_BOOT_SIZE          0x60000 /* 384 KBytes */
51
52
53 #define CONFIG_BOOT_RETRY_TIME          30
54 #define CONFIG_CMDLINE_EDITING
55
56 #define CONFIG_SYS_PROMPT       "U-Boot> "      /* Monitor Command Prompt */
57 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
58 #define CONFIG_SYS_MAXARGS      32              /* max number of command args */
59 #define CONFIG_SYS_PBSIZE       \
60         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
61
62 #define CONFIG_STACKSIZE        (32*1024)       /* regular stack */
63
64 /*
65  * ARM asynchronous clock
66  */
67
68 #define AT91C_MAIN_CLOCK        179404800       /* from 12.288 MHz * 73 / 5 */
69 #define AT91C_MASTER_CLOCK      (AT91C_MAIN_CLOCK / 3)
70 #define CONFIG_SYS_HZ           1000
71 #define CONFIG_SYS_HZ_CLOCK     (AT91C_MASTER_CLOCK / 2)
72
73 #define AT91_SLOW_CLOCK                 32768           /* slow clock */
74
75 #define CONFIG_CMDLINE_TAG              1
76 #define CONFIG_SETUP_MEMORY_TAGS        1
77 #define CONFIG_INITRD_TAG               1
78
79 #define CONFIG_SYS_USE_MAIN_OSCILLATOR  1
80 /* flash */
81 #define CONFIG_SYS_EBI_CFGR_VAL         0x00000000
82 #define CONFIG_SYS_SMC_CSR0_VAL         0x00003284 /* 16bit, 2 TDF, 4 WS */
83
84 /* clocks */
85 #define CONFIG_SYS_PLLAR_VAL            0x20483E05 /* 179.4048 MHz for PCK */
86 #define CONFIG_SYS_PLLBR_VAL            0x104C3E0A /* 47.3088 MHz (for USB) */
87 #define CONFIG_SYS_MCKR_VAL             0x00000202 /* PCK/3 = MCK Clock */
88
89 /*
90  * Size of malloc() pool
91  */
92
93 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 520*1024)
94
95 /*
96  * sdram
97  */
98
99 #define CONFIG_NR_DRAM_BANKS            1
100
101 #define CONFIG_SYS_SDRAM_BASE           0x20000000
102 #define CONFIG_SYS_SDRAM_SIZE           0x04000000  /* 64 megs */
103 #define CONFIG_SYS_INIT_SP_ADDR         0x00204000  /* use internal SRAM */
104
105 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
106 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
107                                         CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
108                                         CONFIG_SYS_MALLOC_LEN)
109
110 #define CONFIG_SYS_PIOC_ASR_VAL         0xFFFF0000 /* PIOC as D16/D31 */
111 #define CONFIG_SYS_PIOC_BSR_VAL         0x00000000
112 #define CONFIG_SYS_PIOC_PDR_VAL         0xFFFF0000
113 #define CONFIG_SYS_EBI_CSA_VAL          0x00000002 /* CS1=SDRAM */
114 #define CONFIG_SYS_SDRC_CR_VAL          0x2188c159 /* set up the SDRAM */
115 #define CONFIG_SYS_SDRAM                0x20000000 /* address of the SDRAM */
116 #define CONFIG_SYS_SDRAM1               0x20000080 /* address of the SDRAM */
117 #define CONFIG_SYS_SDRAM_VAL            0x00000000 /* value written to SDRAM */
118 #define CONFIG_SYS_SDRC_MR_VAL          0x00000002 /* Precharge All */
119 #define CONFIG_SYS_SDRC_MR_VAL1         0x00000004 /* refresh */
120 #define CONFIG_SYS_SDRC_MR_VAL2         0x00000003 /* Load Mode Register */
121 #define CONFIG_SYS_SDRC_MR_VAL3         0x00000000 /* Normal Mode */
122 #define CONFIG_SYS_SDRC_TR_VAL          0x000002E0 /* Write refresh rate */
123
124 /*
125  * Command line configuration
126  */
127
128 #include <config_cmd_default.h>
129
130 #define CONFIG_CMD_BMP
131 #define CONFIG_CMD_DATE
132 #define CONFIG_CMD_DHCP
133 #define CONFIG_CMD_I2C
134 #define CONFIG_CMD_JFFS2
135 #define CONFIG_CMD_MII
136 #define CONFIG_CMD_NAND
137 #define CONFIG_CMD_PING
138 #define CONFIG_I2C_CMD_NO_FLAT
139 #define CONFIG_I2C_CMD_TREE
140
141 #define CONFIG_SYS_LONGHELP
142
143 /*
144  * Filesystems
145  */
146
147 #define CONFIG_JFFS2_NAND               1
148
149 #ifndef CONFIG_JFFS2_CMDLINE
150 #define CONFIG_JFFS2_DEV                "nand0"
151 #define CONFIG_JFFS2_PART_OFFSET        0
152 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
153 #else
154 #define MTDIDS_DEFAULT          "nor0=0,nand0=1"
155 #define MTDPARTS_DEFAULT        "mtdparts="                             \
156                                         "0:"                            \
157                                         "384k(U-Boot),"                 \
158                                         "128k(Env),"                    \
159                                         "128k(Splash),"                 \
160                                         "4M(Kernel),"                   \
161                                         "-(FS)"                         \
162                                         ";"                             \
163                                         "1:"                            \
164                                         "-(jffs2)"
165 #endif /* CONFIG_JFFS2_CMDLINE */
166
167 /*
168  * Hardware drivers
169  */
170
171 /*
172  * UART/CONSOLE
173  */
174
175 #define CONFIG_SYS_BAUDRATE_TABLE       { 115200, 19200, 38400, 57600, 9600 }
176
177 #define CONFIG_BAUDRATE 115200
178 #define CONFIG_AT91RM9200_USART
179 #define CONFIG_DBGU                     /* define DBGU as console */
180
181 /*
182  * network
183  */
184 #define CONFIG_NET_MULTI                1
185
186 #define CONFIG_NET_RETRY_COUNT          10
187 #define CONFIG_RESET_PHY_R              1
188
189 #define CONFIG_DRIVER_AT91EMAC          1
190 #define CONFIG_DRIVER_AT91EMAC_QUIET    1
191 #define CONFIG_SYS_RX_ETH_BUFFER        8
192 #define CONFIG_MII                      1
193
194 /*
195  * BOOTP options
196  */
197 #define CONFIG_BOOTP_BOOTFILESIZE
198 #define CONFIG_BOOTP_BOOTPATH
199 #define CONFIG_BOOTP_GATEWAY
200 #define CONFIG_BOOTP_HOSTNAME
201
202 /*
203  * I2C-Bus
204  */
205
206 #define CONFIG_SYS_I2C_SPEED            50000
207 #define CONFIG_SYS_I2C_SLAVE            0               /* not used */
208
209 #ifndef CONFIG_HARD_I2C
210 #define CONFIG_SOFT_I2C
211
212 /* Software  I2C driver configuration */
213
214 #define AT91_PIN_SDA                    (1<<25)         /* AT91C_PIO_PA25 */
215 #define AT91_PIN_SCL                    (1<<26)         /* AT91C_PIO_PA26 */
216
217 #define CONFIG_SYS_I2C_INIT_BOARD
218
219 #define I2C_INIT        i2c_init_board();
220 #define I2C_ACTIVE      writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
221 #define I2C_TRISTATE    writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
222 #define I2C_READ        ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
223 #define I2C_SDA(bit)                                            \
224         if (bit)                                                \
225                 writel(AT91_PMX_AA_TWD, &pio->pioa.sodr);       \
226         else                                                    \
227                 writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
228 #define I2C_SCL(bit)                                            \
229         if (bit)                                                \
230                 writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr);      \
231         else                                                    \
232                 writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
233
234 #define I2C_DELAY       udelay(2500000/CONFIG_SYS_I2C_SPEED)
235
236 #endif  /* CONFIG_HARD_I2C */
237
238 /* I2C-RTC */
239
240 #ifdef CONFIG_CMD_DATE
241 #define CONFIG_RTC_DS1338
242 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
243 #endif
244
245 /* EEPROM */
246
247 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
248 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
249
250 /* FLASH organization */
251
252 /*  NOR-FLASH */
253 #define CONFIG_FLASH_SHOW_PROGRESS      45
254
255 #define CONFIG_FLASH_CFI_DRIVER 1
256
257 #define PHYS_FLASH_1                    0x10000000
258 #define PHYS_FLASH_SIZE                 0x01000000  /* 16 megs main flash */
259 #define CONFIG_SYS_FLASH_CFI            1
260 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
261
262 #define CONFIG_SYS_FLASH_PROTECTION     1
263 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
264 #define CONFIG_SYS_MAX_FLASH_BANKS      1
265 #define CONFIG_SYS_MAX_FLASH_SECT       512
266 #define CONFIG_SYS_FLASH_ERASE_TOUT     6000
267 #define CONFIG_SYS_FLASH_WRITE_TOUT     2000
268
269 /* NAND */
270
271 #define CONFIG_SYS_NAND_MAX_CHIPS       1
272 #define CONFIG_SYS_MAX_NAND_DEVICE      1
273 #define CONFIG_SYS_NAND_BASE            0x40000000
274 #define CONFIG_SYS_NAND_DBW_8           1
275
276 #define CONFIG_SYS_64BIT_VSPRINTF       1
277
278 /* Status LED's */
279
280 #define CONFIG_STATUS_LED               1
281 #define CONFIG_BOARD_SPECIFIC_LED       1
282
283 #define STATUS_LED_BOOT                 1
284 #define STATUS_LED_ACTIVE               0
285
286 #define STATUS_LED_BIT                  1       /* AT91C_PIO_PD0 green LED */
287 #define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
288 #define STATUS_LED_STATE                STATUS_LED_OFF          /* BLINKING */
289 #define STATUS_LED_BIT1                 2       /* AT91C_PIO_PD1  red LED */
290 #define STATUS_LED_STATE1               STATUS_LED_ON           /* BLINKING */
291 #define STATUS_LED_PERIOD1              (CONFIG_SYS_HZ / 4)
292
293 #define CONFIG_VIDEO                    1
294
295 /* Options */
296
297 #ifdef CONFIG_VIDEO
298
299 #define CONFIG_VIDEO_VCXK                       1
300
301 #define CONFIG_SPLASH_SCREEN                    1
302
303 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       4
304 #define CONFIG_SYS_VCXK_BASE    0x30000000
305
306 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         (1<<3)
307 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        piob
308 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         odr
309
310 #define CONFIG_SYS_VCXK_ENABLE_PIN              (1<<5)
311 #define CONFIG_SYS_VCXK_ENABLE_PORT             piob
312 #define CONFIG_SYS_VCXK_ENABLE_DDR              oer
313
314 #define CONFIG_SYS_VCXK_REQUEST_PIN             (1<<2)
315 #define CONFIG_SYS_VCXK_REQUEST_PORT            piob
316 #define CONFIG_SYS_VCXK_REQUEST_DDR             oer
317
318 #define CONFIG_SYS_VCXK_INVERT_PIN              (1<<4)
319 #define CONFIG_SYS_VCXK_INVERT_PORT             piob
320 #define CONFIG_SYS_VCXK_INVERT_DDR              oer
321
322 #define CONFIG_SYS_VCXK_RESET_PIN               (1<<6)
323 #define CONFIG_SYS_VCXK_RESET_PORT              piob
324 #define CONFIG_SYS_VCXK_RESET_DDR               oer
325
326 #endif  /* CONFIG_VIDEO */
327
328 /* Environment */
329
330 #define CONFIG_BOOTDELAY                5
331
332 #define CONFIG_ENV_IS_IN_FLASH          1
333 #define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0x60000)
334 #define CONFIG_ENV_SIZE                 0x20000 /* sectors are 128K here */
335
336 #define CONFIG_BAUDRATE                 115200
337
338 #define CONFIG_BOOTCOMMAND              "run nfsboot"
339
340 #define CONFIG_NFSBOOTCOMMAND                                           \
341                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
342                 "run bootargsdefaults;"                                 \
343                 "set bootargs $(bootargs) boot=nfs "                    \
344                 ";echo $(bootargs)"                                     \
345         ";bootm"
346
347 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
348         "displaywidth=256\0"                                            \
349         "displayheight=512\0"                                           \
350         "displaybsteps=1023\0"                                          \
351         "ubootaddr=10000000\0"                                          \
352         "splashimage=10080000\0"                                        \
353         "kerneladdr=100A0000\0"                                         \
354         "kernelsize=00400000\0"                                         \
355         "rootfsaddr=104A0000\0"                                         \
356         "copy_addr=21200000\0"                                          \
357         "rootfssize=00B60000\0"                                         \
358         "bootargsdefaults=set bootargs "                                \
359                 "console=ttyS0,115200 "                                 \
360                 "video=vcxk_fb:xres:${displaywidth},"                   \
361                         "yres:${displayheight},"                        \
362                         "bres:${displaybsteps} "                        \
363                 "mem=62M "                                              \
364                 "panic=10 "                                             \
365                 "uboot=\\\"${ver}\\\" "                                 \
366                 "\0"                                                    \
367         "update_kernel=protect off $(kerneladdr) +$(kernelsize);"       \
368                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
369                 "erase $(kerneladdr) +$(kernelsize);"                   \
370                 "cp.b $(fileaddr) $(kerneladdr) $(filesize);"           \
371                 "protect on $(kerneladdr) +$(kernelsize)"               \
372                 "\0"                                                    \
373         "update_root=protect off $(rootfsaddr) +$(rootfssize);"         \
374                 "dhcp $(copy_addr) rfs;"                                \
375                 "erase $(rootfsaddr) +$(rootfssize);"                   \
376                 "cp.b $(fileaddr) $(rootfsaddr) $(filesize);"           \
377                 "\0"                                                    \
378         "update_uboot=protect off 10000000 1005FFFF;"                   \
379                 "dhcp $(copy_addr) u-boot_eb_cpux9k2;"                  \
380                 "erase 10000000 1005FFFF;"                              \
381                 "cp.b $(fileaddr) $(ubootaddr) $(filesize);"            \
382                 "protect on 10000000 1005FFFF;reset\0"                  \
383         "update_splash=protect off $(splashimage) +20000;"              \
384                 "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;"              \
385                 "erase $(splashimage) +20000;"                          \
386                 "cp.b $(fileaddr) 10080000 $(filesize);"                \
387                 "protect on $(splashimage) +20000;reset\0"              \
388         "emergency=run bootargsdefaults;"                               \
389                 "set bootargs $(bootargs) root=initramfs boot=emergency " \
390                 ";bootm $(kerneladdr)\0"                                \
391         "netemergency=run bootargsdefaults;"                            \
392                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
393                 "set bootargs $(bootargs) root=initramfs boot=emergency " \
394                 ";bootm $(copy_addr)\0"                                 \
395         "norboot=run bootargsdefaults;"                                 \
396                 "set bootargs $(bootargs) root=initramfs boot=local "   \
397                 ";bootm $(kerneladdr)\0"                                \
398         "nandboot=run bootargsdefaults;"                                \
399                 "set bootargs $(bootargs) root=initramfs boot=nand "    \
400                 ";bootm $(kerneladdr)\0"                                \
401         " "
402
403 /*--------------------------------------------------------------------------*/
404
405 #endif
406
407 /* EOF */