include/configs/eb_cpu5282.h

   1 /*
   2  * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
   3  *
   4  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _CONFIG_EB_CPU5282_H_
  10 #define _CONFIG_EB_CPU5282_H_
  11
  12 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  13
  14 /*----------------------------------------------------------------------*
  15  * High Level Configuration Options (easy to change)                    *
  16  *----------------------------------------------------------------------*/
  17
  18 #define CONFIG_MCF52x2                  /* define processor family */
  19 #define CONFIG_M5282                    /* define processor type */
  20
  21 #define CONFIG_MISC_INIT_R
  22
  23 #define CONFIG_MCFUART
  24 #define CONFIG_SYS_UART_PORT            (0)
  25 #define CONFIG_BAUDRATE                 115200
  26
  27 #undef  CONFIG_MONITOR_IS_IN_RAM                /* starts uboot direct */
  28
  29 #define CONFIG_BOOTCOMMAND "printenv"
  30
  31 /*----------------------------------------------------------------------*
  32  * Options                                                              *
  33  *----------------------------------------------------------------------*/
  34
  35 #define CONFIG_BOOT_RETRY_TIME  -1
  36 #define CONFIG_RESET_TO_RETRY
  37 #define CONFIG_SPLASH_SCREEN
  38
  39 #define CONFIG_HW_WATCHDOG
  40
  41 #define CONFIG_STATUS_LED
  42 #define CONFIG_BOARD_SPECIFIC_LED
  43 #define STATUS_LED_ACTIVE               0
  44 #define STATUS_LED_BIT                  0x0008  /* Timer7 GPIO */
  45 #define STATUS_LED_BOOT                 0
  46 #define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
  47 #define STATUS_LED_STATE                STATUS_LED_OFF
  48
  49 /*----------------------------------------------------------------------*
  50  * Configuration for environment                                        *
  51  * Environment is in the second sector of the first 256k of flash       *
  52  *----------------------------------------------------------------------*/
  53
  54 #define CONFIG_ENV_ADDR         0xFF040000
  55 #define CONFIG_ENV_SECT_SIZE    0x00020000
  56 #define CONFIG_ENV_IS_IN_FLASH  1
  57
  58 /*
  59  * BOOTP options
  60  */
  61 #define CONFIG_BOOTP_BOOTFILESIZE
  62 #define CONFIG_BOOTP_BOOTPATH
  63 #define CONFIG_BOOTP_GATEWAY
  64 #define CONFIG_BOOTP_HOSTNAME
  65
  66 /*
  67  * Command line configuration.
  68  */
  69 #define CONFIG_CMDLINE_EDITING
  70 #include <config_cmd_default.h>
  71
  72 #undef CONFIG_CMD_LOADB
  73 #define CONFIG_CMD_DATE
  74 #define CONFIG_CMD_DHCP
  75 #define CONFIG_CMD_I2C
  76 #define CONFIG_CMD_LED
  77 #define CONFIG_CMD_MII
  78 #define CONFIG_CMD_NET
  79
  80 #define CONFIG_MCFTMR
  81
  82 #define CONFIG_BOOTDELAY        5
  83 #define CONFIG_SYS_PROMPT       "\nEB+CPU5282> "
  84 #define CONFIG_SYS_LONGHELP     1
  85
  86 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size      */
  87 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  88 #define CONFIG_SYS_MAXARGS      16      /* max number of command args   */
  89 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  90
  91 #define CONFIG_SYS_LOAD_ADDR            0x20000
  92
  93 #define CONFIG_SYS_MEMTEST_START        0x100000
  94 #define CONFIG_SYS_MEMTEST_END          0x400000
  95 /*#define CONFIG_SYS_DRAM_TEST          1 */
  96 #undef CONFIG_SYS_DRAM_TEST
  97
  98 /*----------------------------------------------------------------------*
  99  * Clock and PLL Configuration                                          *
 100  *----------------------------------------------------------------------*/
 101 #define CONFIG_SYS_CLK                  80000000      /* 8MHz * 8 */
 102
 103 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
 104
 105 #define CONFIG_SYS_MFD          0x02    /* PLL Multiplication Factor Devider */
 106 #define CONFIG_SYS_RFD          0x00    /* PLL Reduce Frecuency Devider */
 107
 108 /*----------------------------------------------------------------------*
 109  * Network                                                              *
 110  *----------------------------------------------------------------------*/
 111
 112 #define CONFIG_MCFFEC
 113 #define CONFIG_MII                      1
 114 #define CONFIG_MII_INIT                 1
 115 #define CONFIG_SYS_DISCOVER_PHY
 116 #define CONFIG_SYS_RX_ETH_BUFFER        8
 117 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 118
 119 #define CONFIG_SYS_FEC0_PINMUX          0
 120 #define CONFIG_SYS_FEC0_MIIBASE         CONFIG_SYS_FEC0_IOBASE
 121 #define MCFFEC_TOUT_LOOP                50000
 122
 123 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 124
 125 /*-------------------------------------------------------------------------
 126  * Low Level Configuration Settings
 127  * (address mappings, register initial values, etc.)
 128  * You should know what you are doing if you make changes here.
 129  *-----------------------------------------------------------------------*/
 130
 131 #define CONFIG_SYS_MBAR                 0x40000000
 132
 133 /*-----------------------------------------------------------------------
 134  * Definitions for initial stack pointer and data area (in DPRAM)
 135  *-----------------------------------------------------------------------*/
 136
 137 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 138 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
 139 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 140         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 141 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 142
 143 /*-----------------------------------------------------------------------
 144  * Start addresses for the final memory configuration
 145  * (Set up by the startup code)
 146  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 147  */
 148 #define CONFIG_SYS_SDRAM_BASE0          0x00000000
 149 #define CONFIG_SYS_SDRAM_SIZE0          16      /* SDRAM size in MB */
 150
 151 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_SDRAM_BASE0
 152 #define CONFIG_SYS_SDRAM_SIZE           CONFIG_SYS_SDRAM_SIZE0
 153
 154 #define CONFIG_SYS_MONITOR_LEN          0x20000
 155 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 156 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 157
 158 /*
 159  * For booting Linux, the board info and command line data
 160  * have to be in the first 8 MB of memory, since this is
 161  * the maximum mapped by the Linux kernel during initialization ??
 162  */
 163 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
 164
 165 /*-----------------------------------------------------------------------
 166  * FLASH organization
 167  */
 168 #define CONFIG_FLASH_SHOW_PROGRESS      45
 169
 170 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 171 #define CONFIG_SYS_INT_FLASH_BASE       0xF0000000
 172 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 173
 174 #define CONFIG_SYS_MAX_FLASH_SECT       128
 175 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 176 #define CONFIG_SYS_FLASH_ERASE_TOUT     10000000
 177 #define CONFIG_SYS_FLASH_PROTECTION
 178
 179 #define CONFIG_SYS_FLASH_CFI
 180 #define CONFIG_FLASH_CFI_DRIVER
 181 #define CONFIG_SYS_FLASH_SIZE           16*1024*1024
 182 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 183
 184 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 185
 186 /*-----------------------------------------------------------------------
 187  * Cache Configuration
 188  */
 189 #define CONFIG_SYS_CACHELINE_SIZE       16
 190
 191 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 192                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 193 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 194                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 195 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 196 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 197                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 198                                          CF_ACR_EN | CF_ACR_SM_ALL)
 199 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 200                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 201                                          CF_CACR_EUSP)
 202
 203 /*-----------------------------------------------------------------------
 204  * Memory bank definitions
 205  */
 206
 207 #define CONFIG_SYS_CS0_BASE             0xFF000000
 208 #define CONFIG_SYS_CS0_CTRL             0x00001980
 209 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 210
 211 #define CONFIG_SYS_CS2_BASE             0xE0000000
 212 #define CONFIG_SYS_CS2_CTRL             0x00001980
 213 #define CONFIG_SYS_CS2_MASK             0x000F0001
 214
 215 #define CONFIG_SYS_CS3_BASE             0xE0100000
 216 #define CONFIG_SYS_CS3_CTRL             0x00001980
 217 #define CONFIG_SYS_CS3_MASK             0x000F0001
 218
 219 /*-----------------------------------------------------------------------
 220  * Port configuration
 221  */
 222 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 223 #define CONFIG_SYS_PADDR                0x0000000
 224 #define CONFIG_SYS_PADAT                0x0000000
 225
 226 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 227 #define CONFIG_SYS_PBDDR                0x0000000
 228 #define CONFIG_SYS_PBDAT                0x0000000
 229
 230 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 231 #define CONFIG_SYS_PCDDR                0x0000000
 232 #define CONFIG_SYS_PCDAT                0x0000000
 233
 234 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 235 #define CONFIG_SYS_PCDDR                0x0000000
 236 #define CONFIG_SYS_PCDAT                0x0000000
 237
 238 #define CONFIG_SYS_PASPAR               0x0F0F
 239 #define CONFIG_SYS_PEHLPAR              0xC0
 240 #define CONFIG_SYS_PUAPAR               0x0F
 241 #define CONFIG_SYS_DDRUA                0x05
 242 #define CONFIG_SYS_PJPAR                0xFF
 243
 244 /*-----------------------------------------------------------------------
 245  * I2C
 246  */
 247
 248 #define CONFIG_SYS_I2C
 249 #define CONFIG_SYS_I2C_FSL
 250
 251 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000300
 252 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 253
 254 #define CONFIG_SYS_FSL_I2C_SPEED        100000
 255 #define CONFIG_SYS_FSL_I2C_SLAVE        0
 256
 257 #ifdef CONFIG_CMD_DATE
 258 #define CONFIG_RTC_DS1338
 259 #define CONFIG_I2C_RTC_ADDR             0x68
 260 #endif
 261
 262 /*-----------------------------------------------------------------------
 263  * VIDEO configuration
 264  */
 265
 266 #define CONFIG_VIDEO
 267
 268 #ifdef CONFIG_VIDEO
 269 #define CONFIG_VIDEO_VCXK                       1
 270
 271 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       2
 272 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED          1
 273 #define CONFIG_SYS_VCXK_BASE                    CONFIG_SYS_CS2_BASE
 274
 275 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        MCFGPTB_GPTPORT
 276 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         MCFGPTB_GPTDDR
 277 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         0x0001
 278
 279 #define CONFIG_SYS_VCXK_ENABLE_PORT             MCFGPTB_GPTPORT
 280 #define CONFIG_SYS_VCXK_ENABLE_DDR              MCFGPTB_GPTDDR
 281 #define CONFIG_SYS_VCXK_ENABLE_PIN              0x0002
 282
 283 #define CONFIG_SYS_VCXK_REQUEST_PORT            MCFGPTB_GPTPORT
 284 #define CONFIG_SYS_VCXK_REQUEST_DDR             MCFGPTB_GPTDDR
 285 #define CONFIG_SYS_VCXK_REQUEST_PIN             0x0004
 286
 287 #define CONFIG_SYS_VCXK_INVERT_PORT             MCFGPIO_PORTE
 288 #define CONFIG_SYS_VCXK_INVERT_DDR              MCFGPIO_DDRE
 289 #define CONFIG_SYS_VCXK_INVERT_PIN              MCFGPIO_PORT2
 290
 291 #endif /* CONFIG_VIDEO */
 292 #endif  /* _CONFIG_M5282EVB_H */
 293 /*---------------------------------------------------------------------*/