2 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
4 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #ifndef _CONFIG_EB_CPU5282_H_
26 #define _CONFIG_EB_CPU5282_H_
28 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
30 /*----------------------------------------------------------------------*
31 * High Level Configuration Options (easy to change) *
32 *----------------------------------------------------------------------*/
34 #define CONFIG_MCF52x2 /* define processor family */
35 #define CONFIG_M5282 /* define processor type */
37 #define CONFIG_MISC_INIT_R
39 #define CONFIG_MCFUART
40 #define CONFIG_SYS_UART_PORT (0)
41 #define CONFIG_BAUDRATE 9600
43 #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
45 #define CONFIG_BOOTCOMMAND "printenv"
47 /*----------------------------------------------------------------------*
49 *----------------------------------------------------------------------*/
51 #define CONFIG_BOOT_RETRY_TIME -1
52 #define CONFIG_RESET_TO_RETRY
53 #define CONFIG_SPLASH_SCREEN
55 /*----------------------------------------------------------------------*
56 * Configuration for environment *
57 * Environment is in the second sector of the first 256k of flash *
58 *----------------------------------------------------------------------*/
60 #ifndef CONFIG_MONITOR_IS_IN_RAM
61 #define CONFIG_ENV_ADDR 0xF003C000 /* End of 256K */
62 #define CONFIG_ENV_SECT_SIZE 0x4000
63 #define CONFIG_ENV_IS_IN_FLASH 1
65 #define CONFIG_ENV_ADDR 0xFFE04000
66 #define CONFIG_ENV_SECT_SIZE 0x2000
67 #define CONFIG_ENV_IS_IN_FLASH 1
73 #define CONFIG_BOOTP_BOOTFILESIZE
74 #define CONFIG_BOOTP_BOOTPATH
75 #define CONFIG_BOOTP_GATEWAY
76 #define CONFIG_BOOTP_HOSTNAME
79 * Command line configuration.
81 #include <config_cmd_default.h>
83 #undef CONFIG_CMD_LOADB
84 #define CONFIG_CMD_MII
85 #define CONFIG_CMD_NET
90 #define CONFIG_BOOTDELAY 5
91 #define CONFIG_SYS_HUSH_PARSER
92 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
93 #define CONFIG_SYS_PROMPT "\nEB+CPU5282> "
94 #define CONFIG_SYS_LONGHELP 1
96 #if defined(CONFIG_CMD_KGDB)
97 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
99 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
101 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
102 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
103 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
105 #define CONFIG_SYS_LOAD_ADDR 0x20000
107 #define CONFIG_SYS_MEMTEST_START 0x100000
108 #define CONFIG_SYS_MEMTEST_END 0x400000
109 /*#define CONFIG_SYS_DRAM_TEST 1 */
110 #undef CONFIG_SYS_DRAM_TEST
112 /*----------------------------------------------------------------------*
113 * Clock and PLL Configuration *
114 *----------------------------------------------------------------------*/
115 #define CONFIG_SYS_HZ 10000000
116 #define CONFIG_SYS_CLK 58982400 /* 9,8304MHz * 6 */
118 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
120 #define CONFIG_SYS_MFD 0x01 /* PLL Multiplication Factor Devider */
121 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
123 /*----------------------------------------------------------------------*
125 *----------------------------------------------------------------------*/
127 #define CONFIG_MCFFEC
129 #define CONFIG_MII_INIT 1
130 #define CONFIG_SYS_DISCOVER_PHY
131 #define CONFIG_SYS_RX_ETH_BUFFER 8
132 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
134 #define CONFIG_SYS_FEC0_PINMUX 0
135 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
136 #define MCFFEC_TOUT_LOOP 50000
138 #define CONFIG_ETHADDR 00:CF:52:82:EB:01
139 #define CONFIG_OVERWRITE_ETHADDR_ONCE
141 /*-------------------------------------------------------------------------
142 * Low Level Configuration Settings
143 * (address mappings, register initial values, etc.)
144 * You should know what you are doing if you make changes here.
145 *-----------------------------------------------------------------------*/
147 #define CONFIG_SYS_MBAR 0x40000000
149 /*-----------------------------------------------------------------------
150 * Definitions for initial stack pointer and data area (in DPRAM)
151 *-----------------------------------------------------------------------*/
153 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
154 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
155 #define CONFIG_SYS_GBL_DATA_OFFSET \
156 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
157 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
159 /*-----------------------------------------------------------------------
160 * Start addresses for the final memory configuration
161 * (Set up by the startup code)
162 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
164 #define CONFIG_SYS_SDRAM_BASE1 0x00000000
165 #define CONFIG_SYS_SDRAM_SIZE1 16 /* SDRAM size in MB */
167 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE1
168 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE1
171 /* If M5282 port is fully implemented the monitor base will be behind
172 * the vector table. */
173 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
174 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
176 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
179 #define CONFIG_SYS_MONITOR_LEN 0x20000
180 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
181 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
184 * For booting Linux, the board info and command line data
185 * have to be in the first 8 MB of memory, since this is
186 * the maximum mapped by the Linux kernel during initialization ??
188 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
190 /*-----------------------------------------------------------------------
194 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
195 #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
196 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21
198 #define CONFIG_SYS_MAX_FLASH_SECT 35
199 #define CONFIG_SYS_MAX_FLASH_BANKS 2
200 #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
201 #define CONFIG_SYS_FLASH_PROTECTION
203 /*-----------------------------------------------------------------------
204 * Cache Configuration
206 #define CONFIG_SYS_CACHELINE_SIZE 16
208 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
209 CONFIG_SYS_INIT_RAM_SIZE - 8)
210 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
211 CONFIG_SYS_INIT_RAM_SIZE - 4)
212 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
213 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
214 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
215 CF_ACR_EN | CF_ACR_SM_ALL)
216 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
217 CF_CACR_CEIB | CF_CACR_DBWE | \
220 /*-----------------------------------------------------------------------
221 * Memory bank definitions
224 #define CONFIG_SYS_CS0_BASE 0xFFE00000
225 #define CONFIG_SYS_CS0_CTRL 0x00001980
226 #define CONFIG_SYS_CS0_MASK 0x001F0001
228 #define CONFIG_SYS_CS3_BASE 0xE0000000
229 #define CONFIG_SYS_CS0_CTRL 0x00001980
230 #define CONFIG_SYS_CS3_MASK 0x000F0001
232 /*-----------------------------------------------------------------------
235 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
236 #define CONFIG_SYS_PADDR 0x0000000
237 #define CONFIG_SYS_PADAT 0x0000000
239 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
240 #define CONFIG_SYS_PBDDR 0x0000000
241 #define CONFIG_SYS_PBDAT 0x0000000
243 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
244 #define CONFIG_SYS_PCDDR 0x0000000
245 #define CONFIG_SYS_PCDAT 0x0000000
247 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
248 #define CONFIG_SYS_PCDDR 0x0000000
249 #define CONFIG_SYS_PCDAT 0x0000000
251 #define CONFIG_SYS_PEHLPAR 0xC0
252 #define CONFIG_SYS_PUAPAR 0x0F
253 #define CONFIG_SYS_DDRUA 0x05
254 #define CONFIG_SYS_PJPAR 0xFF
256 /*-----------------------------------------------------------------------
257 * VIDEO configuration
263 #define CONFIG_VIDEO_VCXK 1
265 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
266 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
267 #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS3_BASE
268 #define CONFIG_SYS_VCXK_AUTODETECT 1
270 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
271 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
272 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
274 #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
275 #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
276 #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
278 #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
279 #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
280 #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
282 #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
283 #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
284 #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
286 #endif /* CONFIG_VIDEO */
287 #endif /* _CONFIG_M5282EVB_H */
288 /*---------------------------------------------------------------------*/