3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* ------------------------------------------------------------------------- */
27 * board/config.h - configuration options, board specific
34 * High Level Configuration Options
38 #define CONFIG_MPC824X 1
39 /* #define CONFIG_MPC8240 1 */
40 #define CONFIG_MPC8245 1
41 #define CONFIG_EXALION 1
43 #if defined (CONFIG_MPC8240)
44 /* #warning ---------- eXalion with MPC8240 --------------- */
45 #elif defined (CONFIG_MPC8245)
46 /* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */
47 #elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245)
48 #error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245)
50 #error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
52 /* older kernels need clock in MHz newer in Hz */
53 /* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz */
54 #undef CONFIG_CLOCKS_IN_MHZ
56 #define CONFIG_BOOTDELAY 10
59 /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */
62 * Command line configuration.
64 #include <config_cmd_default.h>
66 #define CONFIG_CMD_FLASH
67 #define CONFIG_CMD_SDRAM
68 #define CONFIG_CMD_I2C
69 #define CONFIG_CMD_IDE
70 #define CONFIG_CMD_FAT
71 #define CONFIG_CMD_ENV
72 #define CONFIG_CMD_PCI
75 /*-----------------------------------------------------------------------
76 * Miscellaneous configurable options
78 #define CFG_LONGHELP 1 /* undef to save memory */
79 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
80 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
81 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
82 #define CFG_MAXARGS 8 /* max number of command args */
83 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
84 #define CFG_LOAD_ADDR 0x00100000 /* default load address */
86 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
88 #define CONFIG_MISC_INIT_R 1
90 /*-----------------------------------------------------------------------
91 * Start addresses for the final memory configuration
92 * (Set up by the startup code)
93 * Please note that CFG_SDRAM_BASE _must_ start at 0
95 #define CFG_SDRAM_BASE 0x00000000
96 #define CFG_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */
97 /* return real value. */
99 #define CFG_RESET_ADDRESS 0xFFF00100
102 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
103 #define CFG_MONITOR_BASE TEXT_BASE
105 /*-----------------------------------------------------------------------
106 * Definitions for initial stack pointer and data area
108 #define CFG_INIT_DATA_SIZE 128
110 #define CFG_INIT_RAM_ADDR 0x40000000
111 #define CFG_INIT_RAM_END 0x1000
112 #define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
114 #define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
115 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
116 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
119 #if defined (CONFIG_MPC8240)
120 #define CFG_FLASH_BASE 0xFFE00000
121 #define CFG_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */
122 #elif defined (CONFIG_MPC8245)
123 #define CFG_FLASH_BASE 0xFFC00000
124 #define CFG_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */
126 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
129 #define CFG_ENV_IS_IN_FLASH 1
130 #define CFG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */
131 #define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Use one Flash sector for enviroment */
132 #define CFG_ENV_ADDR 0xFFFC0000
133 #define CFG_ENV_OFFSET 0 /* starting right at the beginning */
135 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
137 #define CFG_ALT_MEMTEST 1 /* use real memory test */
138 #define CFG_MEMTEST_START 0x00004000 /* memtest works on */
139 #define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
141 #define CFG_EUMB_ADDR 0xFC000000
143 /* #define CFG_ISA_MEM 0xFD000000 */
144 #define CFG_ISA_IO 0xFE000000
146 /*-----------------------------------------------------------------------
149 #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
150 #define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
152 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
153 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
155 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE
156 #define FLASH_BASE1_PRELIM 0
159 /*-----------------------------------------------------------------------
160 * FLASH and environment organization
163 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
164 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
165 #define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
166 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
167 #define CFG_FLASH_INCREMENT 0 /* there is only one bank */
168 #define CFG_FLASH_PROTECTION 1 /* use hardware protection */
169 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
172 /*-----------------------------------------------------------------------
175 #define CONFIG_PCI 1 /* include pci support */
176 #undef CONFIG_PCI_PNP
178 #define CONFIG_NET_MULTI 1 /* Multi ethernet cards support */
180 #define CONFIG_EEPRO100 1
182 #define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */
183 #define PCI_ENET0_IOADDR 0x80000000
184 #define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */
185 #define PCI_ENET1_IOADDR 0x81000000
186 #define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */
187 #define PCI_ENET2_IOADDR 0x82000000
188 #define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */
189 #define PCI_ENET3_IOADDR 0x83000000
191 /*-----------------------------------------------------------------------
192 * NS16550 Configuration
194 #define CFG_NS16550 1
195 #define CFG_NS16550_SERIAL 1
197 #define CONFIG_CONS_INDEX 1
198 #define CONFIG_BAUDRATE 38400
200 #define CFG_NS16550_REG_SIZE 1
202 #if (CONFIG_CONS_INDEX == 1)
203 #define CFG_NS16550_CLK 1843200 /* COM1 only ! */
205 #define CFG_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); })
208 #define CFG_NS16550_COM1 (CFG_ISA_IO + 0x3F8)
209 #define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4500)
210 #define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4600)
212 /*-----------------------------------------------------------------------
213 * select i2c support configuration
215 * Supported configurations are {none, software, hardware} drivers.
216 * If the software driver is chosen, there are some additional
217 * configuration items that the driver uses to drive the port pins.
219 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
220 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
221 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
222 #define CFG_I2C_SLAVE 0x7F
224 /*-----------------------------------------------------------------------
225 * Low Level Configuration Settings
226 * (address mappings, register initial values, etc.)
227 * You should know what you are doing if you make changes here.
231 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
232 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */
234 /*#define CONFIG_133MHZ_DRAM 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!! */
236 #if defined (CONFIG_MPC8245)
237 /* Bit-field values for PMCR2. */
238 #if defined (CONFIG_133MHZ_DRAM)
239 #define CFG_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */
240 #define CFG_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */
243 /* Bit-field values for MIOCR1. */
244 #if !defined (CONFIG_133MHZ_DRAM)
245 #define CFG_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */
247 /* Bit-field values for MIOCR2. */
248 #define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */
249 /* - note bottom 3 bits MUST be 0 */
252 /* Bit-field values for MCCR1. */
253 #define CFG_ROMNAL 7 /*rom/flash next access time */
254 #define CFG_ROMFAL 11 /*rom/flash access time */
256 /* Bit-field values for MCCR2. */
257 #define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */
258 #if defined (CONFIG_133MHZ_DRAM)
259 #define CFG_REFINT 1300 /* no of clock cycles between CBR */
260 #else /* refresh cycles */
261 #define CFG_REFINT 750
264 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
265 #if defined (CONFIG_133MHZ_DRAM)
266 #define CFG_BSTOPRE 1023
268 #define CFG_BSTOPRE 250
271 /* Bit-field values for MCCR3. */
272 /* the following are for SDRAM only */
274 #if defined (CONFIG_133MHZ_DRAM)
275 #define CFG_REFREC 9 /* Refresh to activate interval */
277 #define CFG_REFREC 5 /* Refresh to activate interval */
279 #if defined (CONFIG_MPC8240)
280 #define CFG_RDLAT 2 /* data latency from read command */
283 /* Bit-field values for MCCR4. */
284 #if defined (CONFIG_133MHZ_DRAM)
285 #define CFG_PRETOACT 3 /* Precharge to activate interval */
286 #define CFG_ACTTOPRE 7 /* Activate to Precharge interval */
287 #define CFG_ACTORW 5 /* Activate to R/W */
288 #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
291 #define CFG_PRETOACT 2 /* Precharge to activate interval */
292 #define CFG_ACTTOPRE 3 /* Activate to Precharge interval */
293 #define CFG_ACTORW 3 /* Activate to R/W */
294 #define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
296 #define CFG_PRETOACT 2 /* Precharge to activate interval */
297 #define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
298 #define CFG_ACTORW 3 /* Activate to R/W */
299 #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
301 #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
302 #define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
303 #define CFG_REGDIMM 0
304 #if defined (CONFIG_MPC8240)
305 #define CFG_REGISTERD_TYPE_BUFFER 0
306 #elif defined (CONFIG_MPC8245)
307 #define CFG_REGISTERD_TYPE_BUFFER 1
310 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
314 /*-----------------------------------------------------------------------
316 * only bits 20-29 are actually used from these vales to set the
317 * start/end address the upper two bits will be 0, and the lower 20
318 * bits will be set to 0x00000 for a start address, or 0xfffff for an
321 #define CFG_BANK0_START 0x00000000
322 #define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
323 #define CFG_BANK0_ENABLE 1
324 #define CFG_BANK1_START 0x3ff00000
325 #define CFG_BANK1_END 0x3fffffff
326 #define CFG_BANK1_ENABLE 0
327 #define CFG_BANK2_START 0x3ff00000
328 #define CFG_BANK2_END 0x3fffffff
329 #define CFG_BANK2_ENABLE 0
330 #define CFG_BANK3_START 0x3ff00000
331 #define CFG_BANK3_END 0x3fffffff
332 #define CFG_BANK3_ENABLE 0
333 #define CFG_BANK4_START 0x00000000
334 #define CFG_BANK4_END 0x00000000
335 #define CFG_BANK4_ENABLE 0
336 #define CFG_BANK5_START 0x00000000
337 #define CFG_BANK5_END 0x00000000
338 #define CFG_BANK5_ENABLE 0
339 #define CFG_BANK6_START 0x00000000
340 #define CFG_BANK6_END 0x00000000
341 #define CFG_BANK6_ENABLE 0
342 #define CFG_BANK7_START 0x00000000
343 #define CFG_BANK7_END 0x00000000
344 #define CFG_BANK7_ENABLE 0
346 /*-----------------------------------------------------------------------
347 * Memory bank enable bitmask, specifying which of the banks defined above
348 are actually present. MSB is for bank #7, LSB is for bank #0.
350 #define CFG_BANK_ENABLE 0x01
352 #if defined (CONFIG_MPC8240)
353 #define CFG_ODCR 0xDF /* configures line driver impedances, */
354 /* see 8240 book for bit definitions */
355 #elif defined (CONFIG_MPC8245)
356 #if defined (CONFIG_133MHZ_DRAM)
357 #define CFG_ODCR 0xFE /* configures line driver impedances - 133MHz */
359 #define CFG_ODCR 0xDE /* configures line driver impedances - 66MHz */
362 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
365 #define CFG_PGMAX 0x32 /* how long the 8240 retains the */
366 /* currently accessed page in memory */
367 /* see 8240 book for details */
369 /*-----------------------------------------------------------------------
370 * Block Address Translation (BAT) register settings.
372 /* SDRAM 0 - 256MB */
373 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
374 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
376 /* stack in DCACHE @ 1GB (no backing mem) */
377 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
378 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
381 #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
382 #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
384 /* Flash, config addrs, etc */
385 #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
386 #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
388 #define CFG_DBAT0L CFG_IBAT0L
389 #define CFG_DBAT0U CFG_IBAT0U
390 #define CFG_DBAT1L CFG_IBAT1L
391 #define CFG_DBAT1U CFG_IBAT1U
392 #define CFG_DBAT2L CFG_IBAT2L
393 #define CFG_DBAT2U CFG_IBAT2U
394 #define CFG_DBAT3L CFG_IBAT3L
395 #define CFG_DBAT3U CFG_IBAT3U
398 /*-----------------------------------------------------------------------
399 * Cache Configuration
401 #define CFG_CACHELINE_SIZE 32
402 #if defined(CONFIG_CMD_KGDB)
403 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
407 /*-----------------------------------------------------------------------
408 * Internal Definitions
412 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
413 #define BOOTFLAG_WARM 0x02 /* Software reboot */
416 /* values according to the manual */
417 #define CONFIG_DRAM_50MHZ 1
418 #define CONFIG_SDRAM_50MHZ
421 #define NR_8259_INTS 1
423 /*-----------------------------------------------------------------------
426 #define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
427 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 2 drives per IDE bus */
429 #define CFG_ATA_BASE_ADDR CFG_ISA_IO /* base address */
430 #define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
431 #define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
432 #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
433 #define CFG_ATA_REG_OFFSET 0 /* reg offset */
434 #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
438 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
439 #undef CONFIG_IDE_LED /* no led for ide supported */
440 #undef CONFIG_IDE_RESET /* reset for ide supported... */
441 #undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
443 /*-----------------------------------------------------------------------
444 * DISK Partition support
446 #define CONFIG_DOS_PARTITION
448 /*-----------------------------------------------------------------------
449 * For booting Linux, the board info and command line data
450 * have to be in the first 8 MB of memory, since this is
451 * the maximum mapped by the Linux kernel during initialization.
453 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
455 #endif /* __CONFIG_H */