1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
6 #ifndef _CONFIG_SYNOLOGY_DS414_H
7 #define _CONFIG_SYNOLOGY_DS414_H
10 * High Level Configuration Options (easy to change)
14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
15 * for DDR ECC byte filling in the SPL before loading the main
18 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
21 * Commands configuration
25 #define CONFIG_SYS_I2C
26 #define CONFIG_SYS_I2C_MVTWSI
27 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
28 #define CONFIG_SYS_I2C_SLAVE 0x0
29 #define CONFIG_SYS_I2C_SPEED 100000
31 /* SPI NOR flash default params, used by sf commands */
32 #define CONFIG_SF_DEFAULT_SPEED 1000000
33 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
35 /* Environment in SPI NOR flash */
36 #define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */
37 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
38 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
40 #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
43 #ifndef CONFIG_SPL_BUILD
44 #define CONFIG_PCI_MVEBU
45 #define CONFIG_PCI_SCAN_SHOW
48 /* USB/EHCI/XHCI configuration */
50 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
52 /* FIXME: broken XHCI support
53 * Below defines should enable support for the two rear USB3 ports. Sadly, this
54 * does not work because:
55 * - xhci-pci seems to not support DM_USB, so with that enabled it is not
57 * - USB init fails, controller does not respond in time */
59 #if !defined(CONFIG_USB_XHCI_HCD)
60 #define CONFIG_EHCI_IS_TDI
63 /* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
66 * mv-common.h should be defined after CMD configs since it used them
67 * to enable certain macros
69 #include "mv-common.h"
72 * Memory layout while starting into the bin_hdr via the
75 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
76 * 0x4000.4030 bin_hdr start address
77 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
78 * 0x4007.fffc BootROM stack top
80 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
81 * L2 cache thus cannot be used.
86 #define CONFIG_SPL_TEXT_BASE 0x40004030
87 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
89 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
90 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
92 #ifdef CONFIG_SPL_BUILD
93 #define CONFIG_SYS_MALLOC_SIMPLE
96 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
97 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
99 /* SPL related SPI defines */
100 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
102 /* DS414 bus width is 32bits */
103 #define CONFIG_DDR_32BIT
105 /* Default Environment */
106 #define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm"
107 #define CONFIG_LOADADDR 0x80000
108 #undef CONFIG_PREBOOT /* override preboot for USB and SPI flash init */
109 #define CONFIG_PREBOOT "usb start; sf probe"
111 #endif /* _CONFIG_SYNOLOGY_DS414_H */