ARMV7: AM3517/05: Add support for CraneBoard.
[oweals/u-boot.git] / include / configs / devkit8000.h
1 /*
2  * (C) Copyright 2006-2008
3  * Texas Instruments.
4  * Richard Woodruff <r-woodruff2@ti.com>
5  * Syed Mohammed Khasim <x0khasim@ti.com>
6  *
7  * (C) Copyright 2009
8  * Frederik Kriewitz <frederik@kriewitz.eu>
9  *
10  * Configuration settings for the DevKit8000 board.
11  *
12  * See file CREDITS for list of people who contributed to this
13  * project.
14  *
15  * This program is free software; you can redistribute it and/or
16  * modify it under the terms of the GNU General Public License as
17  * published by the Free Software Foundation; either version 2 of
18  * the License, or (at your option) any later version.
19  *
20  * This program is distributed in the hope that it will be useful,
21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  * GNU General Public License for more details.
24  *
25  * You should have received a copy of the GNU General Public License
26  * along with this program; if not, write to the Free Software
27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28  * MA 02111-1307 USA
29  */
30
31 #ifndef __CONFIG_H
32 #define __CONFIG_H
33
34 /* High Level Configuration Options */
35 #define CONFIG_ARMV7            1       /* This is an ARM V7 CPU core */
36 #define CONFIG_OMAP             1       /* in a TI OMAP core */
37 #define CONFIG_OMAP34XX         1       /* which is a 34XX */
38 #define CONFIG_OMAP3430         1       /* which is in a 3430 */
39 #define CONFIG_OMAP3_DEVKIT8000 1       /* working with DevKit8000 */
40
41 #define CONFIG_SYS_TEXT_BASE    0x80008000
42
43 #define CONFIG_SDRC     /* The chip has SDRC controller */
44
45 #include <asm/arch/cpu.h>               /* get chip and board defs */
46 #include <asm/arch/omap3.h>
47
48 /* Display CPU and Board information */
49 #define CONFIG_DISPLAY_CPUINFO          1
50 #define CONFIG_DISPLAY_BOARDINFO        1
51
52 /* Clock Defines */
53 #define V_OSCK                          26000000        /* Clock output from T2 */
54 #define V_SCLK                          (V_OSCK >> 1)
55
56 #undef CONFIG_USE_IRQ                   /* no support for IRQs */
57 #define CONFIG_MISC_INIT_R
58
59 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
60 #define CONFIG_SETUP_MEMORY_TAGS        1
61 #define CONFIG_INITRD_TAG               1
62 #define CONFIG_REVISION_TAG             1
63
64 /* Size of malloc() pool */
65 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB */
66                                                 /* Sector */
67 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
68                                                 /* initial data */
69
70 /* Hardware drivers */
71
72 /* DDR - I use Micron DDR */
73 #define CONFIG_OMAP3_MICRON_DDR         1
74
75 /* DM9000 */
76 #define CONFIG_NET_MULTI                1
77 #define CONFIG_NET_RETRY_COUNT          20
78 #define CONFIG_DRIVER_DM9000            1
79 #define CONFIG_DM9000_BASE              0x2c000000
80 #define DM9000_IO                       CONFIG_DM9000_BASE
81 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 0x400)
82 #define CONFIG_DM9000_USE_16BIT         1
83 #define CONFIG_DM9000_NO_SROM           1
84 #undef  CONFIG_DM9000_DEBUG
85
86 /* NS16550 Configuration */
87 #define CONFIG_SYS_NS16550
88 #define CONFIG_SYS_NS16550_SERIAL
89 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
90 #define CONFIG_SYS_NS16550_CLK          48000000 /* 48MHz (APLL96/2) */
91
92 /* select serial console configuration */
93 #define CONFIG_CONS_INDEX               3
94 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
95 #define CONFIG_SERIAL3                  3
96 #define CONFIG_BAUDRATE                 115200
97 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
98                                         115200}
99
100 /* MMC */
101 #define CONFIG_MMC                      1
102 #define CONFIG_OMAP3_MMC                1
103 #define CONFIG_DOS_PARTITION            1
104
105 /* I2C */
106 #define CONFIG_HARD_I2C                 1
107 #define CONFIG_SYS_I2C_SPEED            100000
108 #define CONFIG_SYS_I2C_SLAVE            1
109 #define CONFIG_SYS_I2C_BUS              0
110 #define CONFIG_SYS_I2C_BUS_SELECT       1
111 #define CONFIG_DRIVER_OMAP34XX_I2C      1
112
113 /* TWL4030 */
114 #define CONFIG_TWL4030_POWER            1
115 #define CONFIG_TWL4030_LED              1
116
117 /* Board NAND Info */
118 #define CONFIG_SYS_NO_FLASH             /* no NOR flash */
119 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
120 #define MTDIDS_DEFAULT                  "nand0=nand"
121 #define MTDPARTS_DEFAULT                "mtdparts=nand:" \
122                                                 "512k(x-loader)," \
123                                                 "1920k(u-boot)," \
124                                                 "128k(u-boot-env)," \
125                                                 "4m(kernel)," \
126                                                 "-(fs)"
127
128 #define CONFIG_NAND_OMAP_GPMC
129 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
130                                                         /* to access nand */
131 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
132                                                         /* to access nand at */
133                                                         /* CS0 */
134 #define GPMC_NAND_ECC_LP_x16_LAYOUT     1
135
136 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
137                                                         /* devices */
138 #define CONFIG_JFFS2_NAND
139 /* nand device jffs2 lives on */
140 #define CONFIG_JFFS2_DEV                "nand0"
141 /* start of jffs2 partition */
142 #define CONFIG_JFFS2_PART_OFFSET        0x680000
143 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* size of jffs2 */
144                                                         /* partition */
145
146 /* commands to include */
147 #include <config_cmd_default.h>
148
149 #define CONFIG_CMD_DHCP                 /* DHCP support                 */
150 #define CONFIG_CMD_EXT2                 /* EXT2 Support                 */
151 #define CONFIG_CMD_FAT                  /* FAT support                  */
152 #define CONFIG_CMD_I2C                  /* I2C serial bus support       */
153 #define CONFIG_CMD_JFFS2                /* JFFS2 Support                */
154 #define CONFIG_CMD_MMC                  /* MMC support                  */
155 #define CONFIG_CMD_MTDPARTS             /* Enable MTD parts commands    */
156 #define CONFIG_CMD_NAND                 /* NAND support                 */
157 #define CONFIG_CMD_NAND_LOCK_UNLOCK     /* nand (un)lock commands       */
158
159 #undef CONFIG_CMD_FPGA                  /* FPGA configuration Support   */
160 #undef CONFIG_CMD_IMI                   /* iminfo                       */
161
162 /* BOOTP/DHCP options */
163 #define CONFIG_BOOTP_SUBNETMASK
164 #define CONFIG_BOOTP_GATEWAY
165 #define CONFIG_BOOTP_HOSTNAME
166 #define CONFIG_BOOTP_NISDOMAIN
167 #define CONFIG_BOOTP_BOOTPATH
168 #define CONFIG_BOOTP_BOOTFILESIZE
169 #define CONFIG_BOOTP_DNS
170 #define CONFIG_BOOTP_DNS2
171 #define CONFIG_BOOTP_SEND_HOSTNAME
172 #define CONFIG_BOOTP_NTPSERVER
173 #define CONFIG_BOOTP_TIMEOFFSET
174 #undef CONFIG_BOOTP_VENDOREX
175
176 /* Environment information */
177 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
178
179 #define CONFIG_BOOTDELAY                3
180
181 #define CONFIG_EXTRA_ENV_SETTINGS \
182         "loadaddr=0x82000000\0" \
183         "console=ttyS2,115200n8\0" \
184         "vram=12M\0" \
185         "dvimode=1024x768MR-16@60\0" \
186         "defaultdisplay=dvi\0" \
187         "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
188         "kernelopts=rw\0" \
189         "commonargs=" \
190                 "setenv bootargs console=${console} " \
191                 "vram=${vram} " \
192                 "omapfb.mode=dvi:${dvimode} " \
193                 "omapdss.def_disp=${defaultdisplay}\0" \
194         "mmcargs=" \
195                 "run commonargs; " \
196                 "setenv bootargs ${bootargs} " \
197                 "root=/dev/mmcblk0p2 " \
198                 "${kernelopts}\0" \
199         "nandargs=" \
200                 "run commonargs; " \
201                 "setenv bootargs ${bootargs} " \
202                 "omapfb.mode=dvi:${dvimode} " \
203                 "omapdss.def_disp=${defaultdisplay} " \
204                 "root=/dev/mtdblock4 " \
205                 "rootfstype=jffs2 " \
206                 "${kernelopts}\0" \
207         "netargs=" \
208                 "run commonargs; " \
209                 "setenv bootargs ${bootargs} " \
210                 "root=/dev/nfs " \
211                 "nfsroot=${serverip}:${rootpath},${nfsopts} " \
212                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
213                 "${kernelopts} " \
214                 "dnsip1=${dnsip} " \
215                 "dnsip2=${dnsip2}\0" \
216         "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
217         "bootscript=echo Running bootscript from mmc ...; " \
218                 "source ${loadaddr}\0" \
219         "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
220         "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
221         "mmcboot=echo Booting from mmc ...; " \
222                 "run mmcargs; " \
223                 "bootm ${loadaddr}\0" \
224         "nandboot=echo Booting from nand ...; " \
225                 "run nandargs; " \
226                 "nand read ${loadaddr} 280000 400000; " \
227                 "bootm ${loadaddr}\0" \
228         "netboot=echo Booting from network ...; " \
229                 "dhcp ${loadaddr}; " \
230                 "run netargs; " \
231                 "bootm ${loadaddr}\0" \
232         "autoboot=if mmc init 0; then " \
233                         "if run loadbootscript; then " \
234                                 "run bootscript; " \
235                         "else " \
236                                 "if run loaduimage; then " \
237                                         "run mmcboot; " \
238                                 "else run nandboot; " \
239                                 "fi; " \
240                         "fi; " \
241                 "else run nandboot; fi\0"
242
243
244 #define CONFIG_BOOTCOMMAND "run autoboot"
245
246 /* Miscellaneous configurable options */
247 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
248 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
249 #define CONFIG_AUTO_COMPLETE            1
250 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
251 #define CONFIG_SYS_PROMPT               "OMAP3 DevKit8000 # "
252 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
253 /* Print Buffer Size */
254 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
255                                         sizeof(CONFIG_SYS_PROMPT) + 16)
256 #define CONFIG_SYS_MAXARGS              128     /* max number of command args */
257
258 /* Boot Argument Buffer Size */
259 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
260
261 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0 + 0x07000000)
262 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
263                                         0x01000000) /* 16MB */
264
265 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0 + 0x02000000)
266
267 /*
268  * OMAP3 has 12 GP timers, they can be driven by the system clock
269  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
270  * This rate is divided by a local divisor.
271  */
272 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
273 #define CONFIG_SYS_PTV                  2 /* Divisor: 2^(PTV+1) => 8 */
274 #define CONFIG_SYS_HZ                   1000
275
276 /* The stack sizes are set up in start.S using the settings below */
277 #define CONFIG_STACKSIZE        (128 << 10)     /* regular stack 128 KiB */
278 #ifdef CONFIG_USE_IRQ
279 #define CONFIG_STACKSIZE_IRQ            (4 << 10)       /* IRQ stack 4 KiB */
280 #define CONFIG_STACKSIZE_FIQ            (4 << 10)       /* FIQ stack 4 KiB */
281 #endif
282
283 /*  Physical Memory Map  */
284 #define CONFIG_NR_DRAM_BANKS            2 /* CS1 may or may not be populated */
285 #define PHYS_SDRAM_1                    OMAP34XX_SDRC_CS0
286 #define PHYS_SDRAM_1_SIZE               (128 << 20)     /* at least 128 MiB */
287 #define PHYS_SDRAM_2                    OMAP34XX_SDRC_CS1
288
289 /* SDRAM Bank Allocation method */
290 #define SDRC_R_B_C                      1
291
292 /* NAND and environment organization  */
293 #define PISMO1_NAND_SIZE                GPMC_SIZE_128M
294
295 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
296
297 #define CONFIG_ENV_IS_IN_NAND           1
298 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
299
300 #define CONFIG_ENV_OFFSET               boot_flash_off
301
302 #ifndef __ASSEMBLY__
303 extern unsigned int boot_flash_base;
304 extern volatile unsigned int boot_flash_env_addr;
305 extern unsigned int boot_flash_off;
306 extern unsigned int boot_flash_sec;
307 extern unsigned int boot_flash_type;
308 #endif
309
310 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
311 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
312 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
313 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
314                                                          CONFIG_SYS_INIT_RAM_SIZE - \
315                                                          GENERATED_GBL_DATA_SIZE)
316
317 #endif /* __CONFIG_H */