2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
8 * Frederik Kriewitz <frederik@kriewitz.eu>
10 * Configuration settings for the DevKit8000 board.
12 * SPDX-License-Identifier: GPL-2.0+
18 /* High Level Configuration Options */
19 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
22 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
23 * 64 bytes before this address should be set aside for u-boot.img's
24 * header. That is 0x800FFFC0--0x80100000 should not be used for any
28 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
29 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
31 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
32 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
34 /* Physical Memory Map */
35 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
37 #include <configs/ti_omap3_common.h>
39 #define CONFIG_MISC_INIT_R
41 #define CONFIG_REVISION_TAG 1
43 /* Size of malloc() pool */
44 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
46 #undef CONFIG_SYS_MALLOC_LEN
47 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
49 /* Hardware drivers */
51 #define CONFIG_NET_RETRY_COUNT 20
52 #define CONFIG_DRIVER_DM9000 1
53 #define CONFIG_DM9000_BASE 0x2c000000
54 #define DM9000_IO CONFIG_DM9000_BASE
55 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
56 #define CONFIG_DM9000_USE_16BIT 1
57 #define CONFIG_DM9000_NO_SROM 1
58 #undef CONFIG_DM9000_DEBUG
61 #define CONFIG_TWL4030_LED 1
65 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
67 #define CONFIG_JFFS2_NAND
68 /* nand device jffs2 lives on */
69 #define CONFIG_JFFS2_DEV "nand0"
70 /* start of jffs2 partition */
71 #define CONFIG_JFFS2_PART_OFFSET 0x680000
72 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
75 /* BOOTP/DHCP options */
76 #define CONFIG_BOOTP_NISDOMAIN
77 #define CONFIG_BOOTP_BOOTFILESIZE
78 #define CONFIG_BOOTP_DNS2
79 #define CONFIG_BOOTP_SEND_HOSTNAME
80 #define CONFIG_BOOTP_NTPSERVER
81 #define CONFIG_BOOTP_TIMEOFFSET
82 #undef CONFIG_BOOTP_VENDOREX
84 /* Environment information */
85 #define CONFIG_EXTRA_ENV_SETTINGS \
86 "loadaddr=0x82000000\0" \
87 "console=ttyO2,115200n8\0" \
90 "dvimode=1024x768MR-16@60\0" \
91 "defaultdisplay=dvi\0" \
92 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
95 "setenv bootargs console=${console} " \
97 "omapfb.mode=dvi:${dvimode} " \
98 "omapdss.def_disp=${defaultdisplay}\0" \
101 "setenv bootargs ${bootargs} " \
102 "root=/dev/mmcblk0p2 " \
107 "setenv bootargs ${bootargs} " \
108 "omapfb.mode=dvi:${dvimode} " \
109 "omapdss.def_disp=${defaultdisplay} " \
110 "root=/dev/mtdblock4 " \
111 "rootfstype=jffs2 " \
115 "setenv bootargs ${bootargs} " \
117 "nfsroot=${serverip}:${rootpath},${nfsopts} " \
118 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
121 "dnsip2=${dnsip2}\0" \
122 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
123 "bootscript=echo Running bootscript from mmc ...; " \
124 "source ${loadaddr}\0" \
125 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
126 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
127 "mmcboot=echo Booting from mmc ...; " \
129 "bootm ${loadaddr}\0" \
130 "nandboot=echo Booting from nand ...; " \
132 "nand read ${loadaddr} 280000 400000; " \
133 "bootm ${loadaddr}\0" \
134 "netboot=echo Booting from network ...; " \
135 "dhcp ${loadaddr}; " \
137 "bootm ${loadaddr}\0" \
138 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
139 "if run loadbootscript; then " \
142 "if run loaduimage; then " \
144 "else run nandboot; " \
147 "else run nandboot; fi\0"
149 #define CONFIG_BOOTCOMMAND "run autoboot"
151 /* Boot Argument Buffer Size */
152 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
153 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
154 0x01000000) /* 16MB */
156 /* NAND and environment organization */
158 #define CONFIG_ENV_OFFSET 0x260000
161 #define CONFIG_SYS_SRAM_START 0x40200000
162 #define CONFIG_SYS_SRAM_SIZE 0x10000
164 /* Defines for SPL */
166 #undef CONFIG_SPL_TEXT_BASE
167 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
169 /* NAND boot config */
170 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
171 #define CONFIG_SYS_NAND_PAGE_COUNT 64
172 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
173 #define CONFIG_SYS_NAND_OOBSIZE 64
174 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
175 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
176 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
179 #define CONFIG_SYS_NAND_ECCSIZE 512
180 #define CONFIG_SYS_NAND_ECCBYTES 3
181 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
183 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
184 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
186 /* SPL OS boot options */
187 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
189 #undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
190 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
191 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
192 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
193 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
194 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
196 #undef CONFIG_SYS_SPL_ARGS_ADDR
197 #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
199 #endif /* __CONFIG_H */