2 * Configuation settings for the Delta board.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * High Level Configuration Options
30 #define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
31 #define CONFIG_DELTA 1 /* Delta board */
33 /* #define CONFIG_LCD 1 */
35 #define CONFIG_SHARP_LM8V31
37 /* #define CONFIG_MMC 1 */
38 #define BOARD_LATE_INIT 1
40 #undef CONFIG_SKIP_RELOCATE_UBOOT
41 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
44 * Size of malloc() pool
46 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
47 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
52 #undef TURN_ON_ETHERNET
53 #ifdef TURN_ON_ETHERNET
54 # define CONFIG_DRIVER_SMC91111 1
55 # define CONFIG_SMC91111_BASE 0x14000300
56 # define CONFIG_SMC91111_EXT_PHY
57 # define CONFIG_SMC_USE_32_BIT
58 # undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
61 #define CONFIG_HARD_I2C 1 /* required for DA9030 access */
62 #define CFG_I2C_SPEED 400000 /* I2C speed */
63 #define CFG_I2C_SLAVE 1 /* I2C controllers address */
64 #define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */
65 #define CFG_DA9030_EXTON_DELAY 0 /* wait x us after DA9030 reset via EXTON */
66 /* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */
69 * select serial console configuration
71 #define CONFIG_FFUART 1
73 /* allow to overwrite serial and ethaddr */
74 #define CONFIG_ENV_OVERWRITE
76 #define CONFIG_BAUDRATE 115200
78 /* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */
79 #ifdef TURN_ON_ETHERNET
80 # define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
82 # define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
92 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
93 #include <cmd_confdefs.h>
95 #define CONFIG_BOOTDELAY -1
96 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
97 #define CONFIG_NETMASK 255.255.0.0
98 #define CONFIG_IPADDR 192.168.0.21
99 #define CONFIG_SERVERIP 192.168.0.250
100 #define CONFIG_BOOTCOMMAND "bootm 80000"
101 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
102 #define CONFIG_CMDLINE_TAG
103 #define CONFIG_TIMESTAMP
105 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
106 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
107 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
111 * Miscellaneous configurable options
113 #define CFG_HUSH_PARSER 1
114 #define CFG_PROMPT_HUSH_PS2 "> "
116 #define CFG_LONGHELP /* undef to save memory */
117 #ifdef CFG_HUSH_PARSER
118 #define CFG_PROMPT "$ " /* Monitor Command Prompt */
120 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
122 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
123 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
124 #define CFG_MAXARGS 16 /* max number of command args */
125 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
126 #define CFG_DEVICE_NULLDEV 1
128 #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
129 #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
131 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
133 #define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */
135 #define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */
137 /* Monahans Core Frequency */
138 #define CFG_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
139 #define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */
142 /* valid baudrates */
143 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
145 /* #define CFG_MMC_BASE 0xF0000000 */
150 * The stack sizes are set up in start.S using the settings below
152 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
153 #ifdef CONFIG_USE_IRQ
154 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
155 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
159 * Physical Memory Map
161 #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
162 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
163 #define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */
164 #define PHYS_SDRAM_2 0xa1000000 /* SDRAM Bank #2 */
165 #define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */
166 #define PHYS_SDRAM_3 0xa2000000 /* SDRAM Bank #3 */
167 #define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */
168 #define PHYS_SDRAM_4 0xa3000000 /* SDRAM Bank #4 */
169 #define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
171 #define CFG_DRAM_BASE 0xa0000000 /* at CS0 */
172 #define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */
174 #undef CFG_SKIP_DRAM_SCRUB
179 /* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
180 #define CONFIG_NEW_NAND_CODE
181 #define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
182 #undef CFG_NAND1_BASE
184 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
185 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
187 /* nand timeout values */
188 #define CFG_NAND_PROG_ERASE_TO 3000
189 #define CFG_NAND_OTHER_TO 100
190 #define CFG_NAND_SENDCMD_RETRY 3
191 #undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
193 /* NAND Timing Parameters (in ns) */
194 #define NAND_TIMING_tCH 10
195 #define NAND_TIMING_tCS 0
196 #define NAND_TIMING_tWH 20
197 #define NAND_TIMING_tWP 40
199 #define NAND_TIMING_tRH 20
200 #define NAND_TIMING_tRP 40
202 #define NAND_TIMING_tR 11123
203 #define NAND_TIMING_tWHR 100
204 #define NAND_TIMING_tAR 10
207 #define CFG_DFC_DEBUG1 /* usefull */
208 #undef CFG_DFC_DEBUG2 /* noisy */
209 #undef CFG_DFC_DEBUG3 /* extremly noisy */
211 #define CONFIG_MTD_DEBUG
212 #define CONFIG_MTD_DEBUG_VERBOSE 1
214 #define ADDR_COLUMN 1
216 #define ADDR_COLUMN_PAGE 3
218 #define NAND_ChipID_UNKNOWN 0x00
219 #define NAND_MAX_FLOORS 1
220 #define NAND_MAX_CHIPS 1
222 #define CFG_NO_FLASH 1
224 #define CFG_ENV_IS_IN_NAND 1
225 #define CFG_ENV_OFFSET 0x40000
226 #define CFG_ENV_OFFSET_REDUND 0x44000
227 #define CFG_ENV_SIZE 0x4000
229 #endif /* __CONFIG_H */