2 * Configuation settings for the Delta board.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * High Level Configuration Options
30 #define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
31 #define CONFIG_DELTA 1 /* Delta board */
33 /* #define CONFIG_LCD 1 */
35 #define CONFIG_SHARP_LM8V31
37 /* #define CONFIG_MMC 1 */
38 #define BOARD_LATE_INIT 1
40 #undef CONFIG_SKIP_RELOCATE_UBOOT
41 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
44 * Size of malloc() pool
46 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
47 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
53 #undef TURN_ON_ETHERNET
54 #ifdef TURN_ON_ETHERNET
55 # define CONFIG_DRIVER_SMC91111 1
56 # define CONFIG_SMC91111_BASE 0x14000300
57 # define CONFIG_SMC91111_EXT_PHY
58 # define CONFIG_SMC_USE_32_BIT
59 # undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
63 * select serial console configuration
65 #define CONFIG_FFUART 1
67 /* allow to overwrite serial and ethaddr */
68 #define CONFIG_ENV_OVERWRITE
70 #define CONFIG_BAUDRATE 115200
72 /* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */
73 #ifdef TURN_ON_ETHERNET
74 # define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
76 # define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET)
80 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
81 #include <cmd_confdefs.h>
83 #define CONFIG_BOOTDELAY -1
84 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
85 #define CONFIG_NETMASK 255.255.0.0
86 #define CONFIG_IPADDR 192.168.0.21
87 #define CONFIG_SERVERIP 192.168.0.250
88 #define CONFIG_BOOTCOMMAND "bootm 80000"
89 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
90 #define CONFIG_CMDLINE_TAG
91 #define CONFIG_TIMESTAMP
93 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
94 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
95 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
99 * Miscellaneous configurable options
101 #define CFG_HUSH_PARSER 1
102 #define CFG_PROMPT_HUSH_PS2 "> "
104 #define CFG_LONGHELP /* undef to save memory */
105 #ifdef CFG_HUSH_PARSER
106 #define CFG_PROMPT "$ " /* Monitor Command Prompt */
108 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
110 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
111 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
112 #define CFG_MAXARGS 16 /* max number of command args */
113 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
114 #define CFG_DEVICE_NULLDEV 1
116 #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
117 #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
119 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
121 #define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */
123 #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
124 #define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
126 /* valid baudrates */
127 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
129 /* #define CFG_MMC_BASE 0xF0000000 */
134 * The stack sizes are set up in start.S using the settings below
136 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
137 #ifdef CONFIG_USE_IRQ
138 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
139 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
143 * Physical Memory Map
145 #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
146 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
147 #define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */
148 #define PHYS_SDRAM_2 0xa1000000 /* SDRAM Bank #2 */
149 #define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */
150 #define PHYS_SDRAM_3 0xa2000000 /* SDRAM Bank #3 */
151 #define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */
152 #define PHYS_SDRAM_4 0xa3000000 /* SDRAM Bank #4 */
153 #define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
155 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
156 #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
157 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
158 #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
159 #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
161 #define CFG_DRAM_BASE 0xa0000000 /* at CS0 */
162 #define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */
164 #define CFG_SKIP_DRAM_SCRUB 1
166 #define CFG_FLASH_BASE PHYS_FLASH_1
168 #define FPGA_REGS_BASE_PHYSICAL 0x08000000
173 #define CFG_GPSR0_VAL 0x00008000
174 #define CFG_GPSR1_VAL 0x00FC0382
175 #define CFG_GPSR2_VAL 0x0001FFFF
176 #define CFG_GPCR0_VAL 0x00000000
177 #define CFG_GPCR1_VAL 0x00000000
178 #define CFG_GPCR2_VAL 0x00000000
179 #define CFG_GPDR0_VAL 0x0060A800
180 #define CFG_GPDR1_VAL 0x00FF0382
181 #define CFG_GPDR2_VAL 0x0001C000
182 #define CFG_GAFR0_L_VAL 0x98400000
183 #define CFG_GAFR0_U_VAL 0x00002950
184 #define CFG_GAFR1_L_VAL 0x000A9558
185 #define CFG_GAFR1_U_VAL 0x0005AAAA
186 #define CFG_GAFR2_L_VAL 0xA0000000
187 #define CFG_GAFR2_U_VAL 0x00000002
189 #define CFG_PSSR_VAL 0x20
194 #define CFG_MSC0_VAL 0x23F223F2
195 #define CFG_MSC1_VAL 0x3FF1A441
196 #define CFG_MSC2_VAL 0x7FF97FF1
197 #define CFG_MDCNFG_VAL 0x00001AC9
198 #define CFG_MDREFR_VAL 0x00018018
199 #define CFG_MDMRS_VAL 0x00000000
202 * PCMCIA and CF Interfaces
204 #define CFG_MECR_VAL 0x00000000
205 #define CFG_MCMEM0_VAL 0x00010504
206 #define CFG_MCMEM1_VAL 0x00010504
207 #define CFG_MCATT0_VAL 0x00010504
208 #define CFG_MCATT1_VAL 0x00010504
209 #define CFG_MCIO0_VAL 0x00004715
210 #define CFG_MCIO1_VAL 0x00004715
212 #define _LED 0x08000010
213 #define LED_BLANK 0x08000040
216 * FLASH and environment organization
218 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
219 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
221 /* timeout values are in ticks */
222 #define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
223 #define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
225 /* NOTE: many default partitioning schemes assume the kernel starts at the
226 * second sector, not an environment. You have been warned!
228 #define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE
230 #define CFG_ENV_IS_IN_FLASH 1
231 #define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
232 #define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
233 #define CFG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16)
239 #define WHOAMI_OFFSET 0x00
240 #define HEXLED_OFFSET 0x10
241 #define BLANKLED_OFFSET 0x40
242 #define DISCRETELED_OFFSET 0x40
243 #define CNFG_SWITCHES_OFFSET 0x50
244 #define USER_SWITCHES_OFFSET 0x60
245 #define MISC_WR_OFFSET 0x80
246 #define MISC_RD_OFFSET 0x90
247 #define INT_MASK_OFFSET 0xC0
248 #define INT_CLEAR_OFFSET 0xD0
249 #define GP_OFFSET 0x100
251 #endif /* __CONFIG_H */