2 * Configuation settings for the Delta board.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * High Level Configuration Options
30 #define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
31 #define CONFIG_DELTA 1 /* Delta board */
33 /* #define CONFIG_LCD 1 */
35 #define CONFIG_SHARP_LM8V31
37 #define BOARD_LATE_INIT 1
39 #undef CONFIG_SKIP_RELOCATE_UBOOT
40 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
42 /* we will never enable dcache, because we have to setup MMU first */
43 #define CONFIG_SYS_NO_DCACHE
46 * Size of malloc() pool
48 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
49 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
54 #undef TURN_ON_ETHERNET
55 #ifdef TURN_ON_ETHERNET
56 # define CONFIG_DRIVER_SMC91111 1
57 # define CONFIG_SMC91111_BASE 0x14000300
58 # define CONFIG_SMC91111_EXT_PHY
59 # define CONFIG_SMC_USE_32_BIT
60 # undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
63 #define CONFIG_HARD_I2C 1 /* required for DA9030 access */
64 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
65 #define CONFIG_SYS_I2C_SLAVE 1 /* I2C controllers address */
66 #define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */
67 #define CONFIG_SYS_DA9030_EXTON_DELAY 100000 /* wait x us after DA9030 reset via EXTON */
68 #define CONFIG_SYS_I2C_INIT_BOARD 1
69 /* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */
71 #define DELTA_CHECK_KEYBD 1 /* check for keys pressed during boot */
72 #define CONFIG_PREBOOT "\0"
74 #ifdef DELTA_CHECK_KEYBD
75 # define KEYBD_DATALEN 4 /* we have four keys */
76 # define KEYBD_KP_DKIN0 0x1 /* vol+ */
77 # define KEYBD_KP_DKIN1 0x2 /* vol- */
78 # define KEYBD_KP_DKIN2 0x3 /* multi */
79 # define KEYBD_KP_DKIN5 0x4 /* SWKEY_GN */
80 #endif /* DELTA_CHECK_KEYBD */
83 * select serial console configuration
85 #define CONFIG_FFUART 1
87 /* allow to overwrite serial and ethaddr */
88 #define CONFIG_ENV_OVERWRITE
90 #define CONFIG_BAUDRATE 115200
96 #define CONFIG_BOOTP_BOOTFILESIZE
97 #define CONFIG_BOOTP_BOOTPATH
98 #define CONFIG_BOOTP_GATEWAY
99 #define CONFIG_BOOTP_HOSTNAME
103 * Command line configuration.
105 #include <config_cmd_default.h>
107 #ifdef TURN_ON_ETHERNET
109 #define CONFIG_CMD_PING
113 #define CONFIG_CMD_SAVEENV
114 #define CONFIG_CMD_NAND
115 #define CONFIG_CMD_I2C
117 #undef CONFIG_CMD_NET
118 #undef CONFIG_CMD_FLASH
119 #undef CONFIG_CMD_IMLS
124 #define CONFIG_USB_OHCI_NEW 1
125 #define CONFIG_USB_STORAGE 1
126 #define CONFIG_DOS_PARTITION 1
128 #include <asm/arch/pxa-regs.h> /* for OHCI_REGS_BASE */
130 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
131 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
132 #define CONFIG_SYS_USB_OHCI_REGS_BASE OHCI_REGS_BASE
133 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "delta"
134 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
136 #define CONFIG_BOOTDELAY -1
137 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
138 #define CONFIG_NETMASK 255.255.0.0
139 #define CONFIG_IPADDR 192.168.0.21
140 #define CONFIG_SERVERIP 192.168.0.250
141 #define CONFIG_BOOTCOMMAND "bootm 80000"
142 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
143 #define CONFIG_CMDLINE_TAG
144 #define CONFIG_TIMESTAMP
146 #if defined(CONFIG_CMD_KGDB)
147 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
148 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
152 * Miscellaneous configurable options
154 #define CONFIG_SYS_HUSH_PARSER 1
155 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
157 #define CONFIG_SYS_LONGHELP /* undef to save memory */
158 #ifdef CONFIG_SYS_HUSH_PARSER
159 #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
161 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
163 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
164 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
165 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
166 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
167 #define CONFIG_SYS_DEVICE_NULLDEV 1
169 #define CONFIG_SYS_MEMTEST_START 0x80400000 /* memtest works on */
170 #define CONFIG_SYS_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */
172 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
174 #define CONFIG_SYS_HZ 1000
176 /* Monahans Core Frequency */
177 #define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
178 #define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */
181 /* valid baudrates */
182 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
185 #define CONFIG_PXA_MMC
186 #define CONFIG_CMD_MMC
187 #define CONFIG_SYS_MMC_BASE 0xF0000000
193 * The stack sizes are set up in start.S using the settings below
195 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
196 #ifdef CONFIG_USE_IRQ
197 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
198 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
202 * Physical Memory Map
204 #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
205 #define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
206 #define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */
207 #define PHYS_SDRAM_2 0x81000000 /* SDRAM Bank #2 */
208 #define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */
209 #define PHYS_SDRAM_3 0x82000000 /* SDRAM Bank #3 */
210 #define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */
211 #define PHYS_SDRAM_4 0x83000000 /* SDRAM Bank #4 */
212 #define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
214 #define CONFIG_SYS_DRAM_BASE 0x80000000 /* at CS0 */
215 #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB Ram */
217 #undef CONFIG_SYS_SKIP_DRAM_SCRUB
222 #undef CONFIG_NAND_LEGACY
224 #define CONFIG_SYS_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
225 #undef CONFIG_SYS_NAND1_BASE
227 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
228 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
230 /* nand timeout values */
231 #define CONFIG_SYS_NAND_PROG_ERASE_TO 3000
232 #define CONFIG_SYS_NAND_OTHER_TO 100
233 #define CONFIG_SYS_NAND_SENDCMD_RETRY 3
234 #undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
236 /* NAND Timing Parameters (in ns) */
237 #define NAND_TIMING_tCH 10
238 #define NAND_TIMING_tCS 0
239 #define NAND_TIMING_tWH 20
240 #define NAND_TIMING_tWP 40
242 #define NAND_TIMING_tRH 20
243 #define NAND_TIMING_tRP 40
245 #define NAND_TIMING_tR 11123
246 #define NAND_TIMING_tWHR 100
247 #define NAND_TIMING_tAR 10
250 #define CONFIG_SYS_DFC_DEBUG1 /* usefull */
251 #undef CONFIG_SYS_DFC_DEBUG2 /* noisy */
252 #undef CONFIG_SYS_DFC_DEBUG3 /* extremly noisy */
254 #define CONFIG_MTD_DEBUG
255 #define CONFIG_MTD_DEBUG_VERBOSE 1
257 #define ADDR_COLUMN 1
259 #define ADDR_COLUMN_PAGE 3
261 #define NAND_ChipID_UNKNOWN 0x00
262 #define NAND_MAX_FLOORS 1
264 #define CONFIG_SYS_NO_FLASH 1
266 #define CONFIG_ENV_IS_IN_NAND 1
267 #define CONFIG_ENV_OFFSET 0x40000
268 #define CONFIG_ENV_OFFSET_REDUND 0x44000
269 #define CONFIG_ENV_SIZE 0x4000
271 #endif /* __CONFIG_H */