2 * Configuation settings for the Delta board.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * High Level Configuration Options
30 #define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
31 #define CONFIG_DELTA 1 /* Delta board */
33 /* #define CONFIG_LCD 1 */
35 #define CONFIG_SHARP_LM8V31
37 /* #define CONFIG_MMC 1 */
38 #define BOARD_LATE_INIT 1
40 #undef CONFIG_SKIP_RELOCATE_UBOOT
41 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
44 * Size of malloc() pool
46 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
47 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
53 #undef TURN_ON_ETHERNET
54 #ifdef TURN_ON_ETHERNET
55 # define CONFIG_DRIVER_SMC91111 1
56 # define CONFIG_SMC91111_BASE 0x14000300
57 # define CONFIG_SMC91111_EXT_PHY
58 # define CONFIG_SMC_USE_32_BIT
59 # undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
63 * select serial console configuration
65 #define CONFIG_FFUART 1
67 /* allow to overwrite serial and ethaddr */
68 #define CONFIG_ENV_OVERWRITE
70 #define CONFIG_BAUDRATE 115200
72 /* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */
73 #ifdef TURN_ON_ETHERNET
74 # define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
76 # define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_ENV | CFG_CMD_NAND) \
77 & ~(CFG_CMD_NET | CFG_CMD_FLASH | CFG_CMD_IMLS))
81 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
82 #include <cmd_confdefs.h>
84 #define CONFIG_BOOTDELAY -1
85 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
86 #define CONFIG_NETMASK 255.255.0.0
87 #define CONFIG_IPADDR 192.168.0.21
88 #define CONFIG_SERVERIP 192.168.0.250
89 #define CONFIG_BOOTCOMMAND "bootm 80000"
90 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
91 #define CONFIG_CMDLINE_TAG
92 #define CONFIG_TIMESTAMP
94 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
95 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
96 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
100 * Miscellaneous configurable options
102 #define CFG_HUSH_PARSER 1
103 #define CFG_PROMPT_HUSH_PS2 "> "
105 #define CFG_LONGHELP /* undef to save memory */
106 #ifdef CFG_HUSH_PARSER
107 #define CFG_PROMPT "$ " /* Monitor Command Prompt */
109 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
111 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
112 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
113 #define CFG_MAXARGS 16 /* max number of command args */
114 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
115 #define CFG_DEVICE_NULLDEV 1
117 #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
118 #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
120 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
122 #define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */
124 #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
125 #define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
127 /* valid baudrates */
128 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
130 /* #define CFG_MMC_BASE 0xF0000000 */
135 * The stack sizes are set up in start.S using the settings below
137 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
138 #ifdef CONFIG_USE_IRQ
139 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
140 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
144 * Physical Memory Map
146 #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
147 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
148 #define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */
149 #define PHYS_SDRAM_2 0xa1000000 /* SDRAM Bank #2 */
150 #define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */
151 #define PHYS_SDRAM_3 0xa2000000 /* SDRAM Bank #3 */
152 #define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */
153 #define PHYS_SDRAM_4 0xa3000000 /* SDRAM Bank #4 */
154 #define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
156 #define CFG_DRAM_BASE 0xa0000000 /* at CS0 */
157 #define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */
159 #undef CFG_SKIP_DRAM_SCRUB
164 /* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
165 #define CONFIG_NEW_NAND_CODE
166 #define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
167 #undef CFG_NAND1_BASE
169 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
170 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
171 #define SECTORSIZE 512
172 #define NAND_DELAY_US 25 /* mk@tbd: could be 0, I guess */
174 /* nand timeout values */
175 #define CFG_NAND_PROG_ERASE_TO 3000
176 #define CFG_NAND_OTHER_TO 100
177 #define CFG_NAND_SENDCMD_RETRY 3
178 #undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
180 /* NAND Timing Parameters (in ns) */
181 #define NAND_TIMING_tCH 10
182 #define NAND_TIMING_tCS 0
183 #define NAND_TIMING_tWH 20
184 #define NAND_TIMING_tWP 40
186 #define NAND_TIMING_tRH 20
187 #define NAND_TIMING_tRP 40
189 #define NAND_TIMING_tR 11123
190 /* #define NAND_TIMING_tWHR 110 */
191 #define NAND_TIMING_tWHR 100
192 #define NAND_TIMING_tAR 10
195 #define CFG_DFC_DEBUG1 /* usefull */
196 #undef CFG_DFC_DEBUG2 /* noisy */
197 #undef CFG_DFC_DEBUG3 /* extremly noisy */
199 #define CONFIG_MTD_DEBUG
200 #define CONFIG_MTD_DEBUG_VERBOSE 1
202 #define ADDR_COLUMN 1
204 #define ADDR_COLUMN_PAGE 3
206 #define NAND_ChipID_UNKNOWN 0x00
207 #define NAND_MAX_FLOORS 1
208 #define NAND_MAX_CHIPS 1
210 #define CFG_NO_FLASH 1
212 /* these are required by the environment code */
213 #define PHYS_FLASH_1 CFG_NAND0_BASE /* Flash Bank #1 */
214 #define PHYS_FLASH_SIZE 0x04000000 /* 64 MB */
215 #define PHYS_FLASH_BANK_SIZE 0x04000000 /* 64 MB Banks */
216 #define PHYS_FLASH_SECT_SIZE (SECTORSIZE*1024) /* KB sectors (x2) */
222 #define CFG_GPSR0_VAL 0x00008000
223 #define CFG_GPSR1_VAL 0x00FC0382
224 #define CFG_GPSR2_VAL 0x0001FFFF
225 #define CFG_GPCR0_VAL 0x00000000
226 #define CFG_GPCR1_VAL 0x00000000
227 #define CFG_GPCR2_VAL 0x00000000
228 #define CFG_GPDR0_VAL 0x0060A800
229 #define CFG_GPDR1_VAL 0x00FF0382
230 #define CFG_GPDR2_VAL 0x0001C000
231 #define CFG_GAFR0_L_VAL 0x98400000
232 #define CFG_GAFR0_U_VAL 0x00002950
233 #define CFG_GAFR1_L_VAL 0x000A9558
234 #define CFG_GAFR1_U_VAL 0x0005AAAA
235 #define CFG_GAFR2_L_VAL 0xA0000000
236 #define CFG_GAFR2_U_VAL 0x00000002
238 #define CFG_PSSR_VAL 0x20
243 #define CFG_MSC0_VAL 0x23F223F2
244 #define CFG_MSC1_VAL 0x3FF1A441
245 #define CFG_MSC2_VAL 0x7FF97FF1
246 #define CFG_MDCNFG_VAL 0x00001AC9
247 #define CFG_MDREFR_VAL 0x00018018
248 #define CFG_MDMRS_VAL 0x00000000
251 * PCMCIA and CF Interfaces
253 #define CFG_MECR_VAL 0x00000000
254 #define CFG_MCMEM0_VAL 0x00010504
255 #define CFG_MCMEM1_VAL 0x00010504
256 #define CFG_MCATT0_VAL 0x00010504
257 #define CFG_MCATT1_VAL 0x00010504
258 #define CFG_MCIO0_VAL 0x00004715
259 #define CFG_MCIO1_VAL 0x00004715
261 #define _LED 0x08000010
262 #define LED_BLANK 0x08000040
265 * FLASH and environment organization
268 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
269 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
271 /* timeout values are in ticks */
272 #define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
273 #define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
276 /* NOTE: many default partitioning schemes assume the kernel starts at the
277 * second sector, not an environment. You have been warned!
279 #define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE
280 #endif /* #ifndef CFG_NO_FLASH */
282 /* #define CFG_ENV_IS_NOWHERE */
283 #define CFG_ENV_IS_IN_NAND 1
284 #define CFG_ENV_OFFSET 0x40000
285 #define CFG_ENV_SIZE 0x4000
287 #endif /* __CONFIG_H */