2 * (C) Copyright 2001, 2002
3 * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* ------------------------------------------------------------------------- */
27 * board/config.h - configuration options, board specific
36 #define CONFIG_BOOTARGS \
37 "console=ttyS0,9600 init=/linuxrc " \
38 "root=/dev/nfs rw nfsroot=192.168.0.1:" \
40 "ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
41 "255.255.255.0:debris:eth0:none " \
42 "mtdparts=phys:12m(root),-(kernel)"
45 #define CONFIG_BOOTCOMMAND \
46 "tftp 800000 pImage; " \
47 "setenv bootargs console=ttyS0,9600 init=/linuxrc " \
48 "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
49 "ip=$(ipaddr):$(serverip):$(gatewayip):" \
50 "$(netmask):$(hostname):eth0:none " \
51 "mtdparts=phys:12m(root),-(kernel); " \
55 #define CONFIG_BOOTDELAY 5 /* autoboot 5s */
58 #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
61 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
67 #undef CONFIG_ETH2ADDR
70 #undef CONFIG_ETH3ADDR
73 #define CONFIG_IPADDR 192.168.0.2
76 #define CONFIG_SERVERIP 192.168.0.1
82 #define CONFIG_ROOTPATH /tftpboot/target
85 #define CONFIG_GATEWAYIP 192.168.0.1
88 #define CONFIG_NETMASK 255.255.255.0
91 #define CONFIG_HOSTNAME debris
94 #define CONFIG_BOOTFILE pImage
97 #define CONFIG_LOADADDR 800000
100 #undef CONFIG_PREBOOT
103 #undef CONFIG_CLOCKS_IN_MHZ
107 * High Level Configuration Options
111 #define CONFIG_MPC824X 1
112 #define CONFIG_MPC8245 1
113 #define CONFIG_DEBRIS 1
121 #define CONFIG_CONS_INDEX 1
122 #define CONFIG_BAUDRATE 9600
123 #define CONFIG_DRAM_SPEED 100 /* MHz */
125 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
140 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
141 #include <cmd_confdefs.h>
145 * Miscellaneous configurable options
147 #define CFG_LONGHELP 1 /* undef to save memory */
148 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
149 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
150 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
151 #define CFG_MAXARGS 16 /* max number of command args */
152 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
153 #define CFG_LOAD_ADDR 0x00100000 /* default load address */
154 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
156 /*-----------------------------------------------------------------------
158 *-----------------------------------------------------------------------
160 #define CONFIG_PCI /* include pci support */
161 #define CONFIG_PCI_PNP
163 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
164 #define CONFIG_EEPRO100
165 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
166 #define CONFIG_EEPRO100_SROM_WRITE
168 #define PCI_ENET0_IOADDR 0x80000000
169 #define PCI_ENET0_MEMADDR 0x80000000
170 #define PCI_ENET1_IOADDR 0x81000000
171 #define PCI_ENET1_MEMADDR 0x81000000
172 /*-----------------------------------------------------------------------
173 * Start addresses for the final memory configuration
174 * (Set up by the startup code)
175 * Please note that CFG_SDRAM_BASE _must_ start at 0
177 #define CFG_SDRAM_BASE 0x00000000
178 #define CFG_MAX_RAM_SIZE 0x10000000
180 #define CFG_RESET_ADDRESS 0xFFF00100
182 #if defined (USE_DINK32)
183 #define CFG_MONITOR_LEN 0x00040000
184 #define CFG_MONITOR_BASE 0x00090000
185 #define CFG_RAMBOOT 1
186 #define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
187 #define CFG_INIT_RAM_END 0x10000
188 #define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
189 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
190 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
193 #define CFG_MONITOR_LEN 0x00040000
194 #define CFG_MONITOR_BASE TEXT_BASE
196 /*#define CFG_GBL_DATA_SIZE 256*/
197 #define CFG_GBL_DATA_SIZE 128
199 #define CFG_INIT_RAM_ADDR 0x40000000
200 #define CFG_INIT_RAM_END 0x1000
201 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
205 #define CFG_FLASH_BASE 0x7C000000
206 #define CFG_FLASH_SIZE (16*1024*1024) /* debris has tiny eeprom */
208 #define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
210 #define CFG_MEMTEST_START 0x00000000 /* memtest works on */
211 #define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
213 #define CFG_EUMB_ADDR 0xFC000000
215 #define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
216 #define CFG_FLASH_RANGE_SIZE 0x01000000
217 #define FLASH_BASE0_PRELIM 0x7C000000 /* debris flash */
219 #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
220 #define CFG_JFFS2_NUM_BANKS 1
222 #define CFG_ENV_IS_IN_NVRAM 1
223 #define CONFIG_ENV_OVERWRITE 1
224 #define CFG_NVRAM_ACCESS_ROUTINE 1
225 #define CFG_ENV_ADDR 0xFF000000 /* right at the start of NVRAM */
226 #define CFG_ENV_SIZE 0x400 /* Size of the Environment - 8K */
227 #define CFG_ENV_OFFSET 0 /* starting right at the beginning */
229 #define CFG_NVRAM_BASE_ADDR 0xff000000
232 * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS =
233 * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
235 #define CFG_NVRAM_VXWORKS_OFFS 0x6900
238 * select i2c support configuration
240 * Supported configurations are {none, software, hardware} drivers.
241 * If the software driver is chosen, there are some additional
242 * configuration items that the driver uses to drive the port pins.
244 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
245 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
246 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
247 #define CFG_I2C_SLAVE 0x7F
249 #ifdef CONFIG_SOFT_I2C
250 #error "Soft I2C is not configured properly. Please review!"
251 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
252 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
253 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
254 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
255 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
256 else iop->pdat &= ~0x00010000
257 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
258 else iop->pdat &= ~0x00020000
259 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
260 #endif /* CONFIG_SOFT_I2C */
262 #define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
263 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
264 #define CFG_EEPROM_PAGE_WRITE_BITS 3
265 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
267 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
268 #define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM }
270 /*-----------------------------------------------------------------------
271 * Definitions for initial stack pointer and data area (in DPRAM)
275 * NS16550 Configuration
278 #define CFG_NS16550_SERIAL
280 #define CFG_NS16550_REG_SIZE 1
282 #define CFG_NS16550_CLK 7372800
284 #define CFG_NS16550_COM1 0xFF080000
285 #define CFG_NS16550_COM2 (CFG_NS16550_COM1 + 8)
286 #define CFG_NS16550_COM3 (CFG_NS16550_COM1 + 16)
287 #define CFG_NS16550_COM4 (CFG_NS16550_COM1 + 24)
290 * Low Level Configuration Settings
291 * (address mappings, register initial values, etc.)
292 * You should know what you are doing if you make changes here.
295 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
296 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
298 #define CFG_DLL_EXTEND 0x00
299 #define CFG_PCI_HOLD_DEL 0x20
301 #define CFG_ROMNAL 15 /* rom/flash next access time */
302 #define CFG_ROMFAL 31 /* rom/flash access time */
304 #define CFG_REFINT 430 /* # of clocks between CBR refresh cycles */
306 #define CFG_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
308 /* the following are for SDRAM only*/
309 #define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
310 #define CFG_REFREC 8 /* Refresh to activate interval */
311 #define CFG_RDLAT 4 /* data latency from read command */
312 #define CFG_PRETOACT 3 /* Precharge to activate interval */
313 #define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
314 #define CFG_ACTORW 3 /* Activate to R/W */
315 #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
316 #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
318 #define CFG_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
321 #define CFG_REGISTERD_TYPE_BUFFER 1
323 #define CFG_REGDIMM 0
326 /* memory bank settings*/
328 * only bits 20-29 are actually used from these vales to set the
329 * start/end address the upper two bits will be 0, and the lower 20
330 * bits will be set to 0x00000 for a start address, or 0xfffff for an
333 #define CFG_BANK0_START 0x00000000
334 #define CFG_BANK0_END (0x4000000 - 1)
335 #define CFG_BANK0_ENABLE 1
336 #define CFG_BANK1_START 0x04000000
337 #define CFG_BANK1_END (0x8000000 - 1)
338 #define CFG_BANK1_ENABLE 1
339 #define CFG_BANK2_START 0x3ff00000
340 #define CFG_BANK2_END 0x3fffffff
341 #define CFG_BANK2_ENABLE 0
342 #define CFG_BANK3_START 0x3ff00000
343 #define CFG_BANK3_END 0x3fffffff
344 #define CFG_BANK3_ENABLE 0
345 #define CFG_BANK4_START 0x00000000
346 #define CFG_BANK4_END 0x00000000
347 #define CFG_BANK4_ENABLE 0
348 #define CFG_BANK5_START 0x00000000
349 #define CFG_BANK5_END 0x00000000
350 #define CFG_BANK5_ENABLE 0
351 #define CFG_BANK6_START 0x00000000
352 #define CFG_BANK6_END 0x00000000
353 #define CFG_BANK6_ENABLE 0
354 #define CFG_BANK7_START 0x00000000
355 #define CFG_BANK7_END 0x00000000
356 #define CFG_BANK7_ENABLE 0
358 * Memory bank enable bitmask, specifying which of the banks defined above
359 are actually present. MSB is for bank #7, LSB is for bank #0.
361 #define CFG_BANK_ENABLE 0x01
363 #define CFG_ODCR 0x75 /* configures line driver impedances, */
364 /* see 8240 book for bit definitions */
365 #define CFG_PGMAX 0x32 /* how long the 8240 retains the */
366 /* currently accessed page in memory */
367 /* see 8240 book for details */
369 /* SDRAM 0 - 256MB */
370 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
371 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
373 /* stack in DCACHE @ 1GB (no backing mem) */
374 #if defined(USE_DINK32)
375 #define CFG_IBAT1L (0x40000000 | BATL_PP_00 )
376 #define CFG_IBAT1U (0x40000000 | BATU_BL_128K )
378 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
379 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
383 #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
384 #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
386 /* Flash, config addrs, etc */
387 #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
388 #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
390 #define CFG_DBAT0L CFG_IBAT0L
391 #define CFG_DBAT0U CFG_IBAT0U
392 #define CFG_DBAT1L CFG_IBAT1L
393 #define CFG_DBAT1U CFG_IBAT1U
394 #define CFG_DBAT2L CFG_IBAT2L
395 #define CFG_DBAT2U CFG_IBAT2U
396 #define CFG_DBAT3L CFG_IBAT3L
397 #define CFG_DBAT3U CFG_IBAT3U
400 * For booting Linux, the board info and command line data
401 * have to be in the first 8 MB of memory, since this is
402 * the maximum mapped by the Linux kernel during initialization.
404 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
405 /*-----------------------------------------------------------------------
408 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
409 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
411 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
412 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
414 /*-----------------------------------------------------------------------
415 * Cache Configuration
417 #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
418 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
419 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
424 * Internal Definitions
428 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
429 #define BOOTFLAG_WARM 0x02 /* Software reboot */
432 /* values according to the manual */
434 #define CONFIG_DRAM_50MHZ 1
435 #define CONFIG_SDRAM_50MHZ
437 #define CONFIG_DISK_SPINUP_TIME 1000000
439 #endif /* __CONFIG_H */