2 * (C) Copyright 2001, 2002
3 * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
5 * SPDX-License-Identifier: GPL-2.0+
8 /* ------------------------------------------------------------------------- */
11 * board/config.h - configuration options, board specific
17 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
22 #define CONFIG_BOOTARGS \
23 "console=ttyS0,9600 init=/linuxrc " \
24 "root=/dev/nfs rw nfsroot=192.168.0.1:" \
26 "ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
27 "255.255.255.0:debris:eth0:none " \
28 "mtdparts=phys:12m(root),-(kernel)"
31 #define CONFIG_BOOTCOMMAND \
32 "tftp 800000 pImage; " \
33 "setenv bootargs console=ttyS0,9600 init=/linuxrc " \
34 "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
35 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
36 "${netmask}:${hostname}:eth0:none " \
37 "mtdparts=phys:12m(root),-(kernel); " \
41 #define CONFIG_BOOTDELAY 5 /* autoboot 5s */
44 #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
47 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
53 #undef CONFIG_ETH2ADDR
56 #undef CONFIG_ETH3ADDR
59 #define CONFIG_IPADDR 192.168.0.2
62 #define CONFIG_SERVERIP 192.168.0.1
65 #undef CONFIG_SYS_AUTOLOAD
68 #define CONFIG_ROOTPATH "/tftpboot/target"
71 #define CONFIG_GATEWAYIP 192.168.0.1
74 #define CONFIG_NETMASK 255.255.255.0
77 #define CONFIG_HOSTNAME debris
80 #define CONFIG_BOOTFILE "pImage"
83 #define CONFIG_LOADADDR 800000
89 #undef CONFIG_CLOCKS_IN_MHZ
93 * High Level Configuration Options
97 #define CONFIG_MPC8245 1
98 #define CONFIG_DEBRIS 1
106 #define CONFIG_CONS_INDEX 1
107 #define CONFIG_BAUDRATE 9600
108 #define CONFIG_DRAM_SPEED 100 /* MHz */
114 #define CONFIG_BOOTP_BOOTFILESIZE
115 #define CONFIG_BOOTP_BOOTPATH
116 #define CONFIG_BOOTP_GATEWAY
117 #define CONFIG_BOOTP_HOSTNAME
121 * Command line configuration.
123 #include <config_cmd_default.h>
125 #define CONFIG_CMD_ASKENV
126 #define CONFIG_CMD_CACHE
127 #define CONFIG_CMD_DATE
128 #define CONFIG_CMD_DHCP
129 #define CONFIG_CMD_DIAG
130 #define CONFIG_CMD_EEPROM
131 #define CONFIG_CMD_ELF
132 #define CONFIG_CMD_I2C
133 #define CONFIG_CMD_JFFS2
134 #define CONFIG_CMD_KGDB
135 #define CONFIG_CMD_PCI
136 #define CONFIG_CMD_PING
137 #define CONFIG_CMD_SAVES
138 #define CONFIG_CMD_SDRAM
142 * Miscellaneous configurable options
144 #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
145 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
146 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
147 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
148 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
149 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
151 /*-----------------------------------------------------------------------
153 *-----------------------------------------------------------------------
155 #define CONFIG_PCI /* include pci support */
156 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
157 #define CONFIG_PCI_PNP
159 #define CONFIG_EEPRO100
160 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
161 #define CONFIG_EEPRO100_SROM_WRITE
163 #define PCI_ENET0_IOADDR 0x80000000
164 #define PCI_ENET0_MEMADDR 0x80000000
165 #define PCI_ENET1_IOADDR 0x81000000
166 #define PCI_ENET1_MEMADDR 0x81000000
167 /*-----------------------------------------------------------------------
168 * Start addresses for the final memory configuration
169 * (Set up by the startup code)
170 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
172 #define CONFIG_SYS_SDRAM_BASE 0x00000000
173 #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
174 #define CONFIG_VERY_BIG_RAM
176 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
178 #if defined (USE_DINK32)
179 #define CONFIG_SYS_MONITOR_LEN 0x00040000
180 #define CONFIG_SYS_MONITOR_BASE 0x00090000
181 #define CONFIG_SYS_RAMBOOT 1
182 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
183 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
184 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
185 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
187 #undef CONFIG_SYS_RAMBOOT
188 #define CONFIG_SYS_MONITOR_LEN 0x00040000
189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
192 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
193 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
194 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
198 #define CONFIG_SYS_FLASH_BASE 0x7C000000
199 #define CONFIG_SYS_FLASH_SIZE (16*1024*1024) /* debris has tiny eeprom */
201 #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
203 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
204 #define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
206 #define CONFIG_SYS_EUMB_ADDR 0xFC000000
208 #define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
209 #define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
210 #define FLASH_BASE0_PRELIM 0x7C000000 /* debris flash */
216 /* No command line, one static partition, whole device */
217 #undef CONFIG_CMD_MTDPARTS
218 #define CONFIG_JFFS2_DEV "nor0"
219 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
220 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
222 /* mtdparts command line support */
224 /* Use first bank for JFFS2, second bank contains U-Boot.
226 * Note: fake mtd_id's used, no linux mtd map file.
229 #define CONFIG_CMD_MTDPARTS
230 #define MTDIDS_DEFAULT "nor0=debris-0"
231 #define MTDPARTS_DEFAULT "mtdparts=debris-0:-(jffs2)"
234 #define CONFIG_ENV_IS_IN_NVRAM 1
235 #define CONFIG_ENV_OVERWRITE 1
236 #define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
237 #define CONFIG_ENV_ADDR 0xFF000000 /* right at the start of NVRAM */
238 #define CONFIG_ENV_SIZE 0x400 /* Size of the Environment - 8K */
239 #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
241 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xff000000
244 * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS =
245 * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
247 #define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900
250 * select i2c support configuration
252 * Supported configurations are {none, software, hardware} drivers.
253 * If the software driver is chosen, there are some additional
254 * configuration items that the driver uses to drive the port pins.
256 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
257 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
258 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
259 #define CONFIG_SYS_I2C_SLAVE 0x7F
261 #ifdef CONFIG_SYS_I2C_SOFT
262 #error "Soft I2C is not configured properly. Please review!"
263 #define CONFIG_SYS_I2C
264 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
265 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
266 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
267 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
268 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
269 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
270 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
271 else iop->pdat &= ~0x00010000
272 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
273 else iop->pdat &= ~0x00020000
274 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
275 #endif /* CONFIG_SYS_I2C_SOFT */
277 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
278 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
279 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
280 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
282 #define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
284 /*-----------------------------------------------------------------------
285 * Definitions for initial stack pointer and data area (in DPRAM)
289 * NS16550 Configuration
291 #define CONFIG_SYS_NS16550
292 #define CONFIG_SYS_NS16550_SERIAL
294 #define CONFIG_SYS_NS16550_REG_SIZE 1
296 #define CONFIG_SYS_NS16550_CLK 7372800
298 #define CONFIG_SYS_NS16550_COM1 0xFF080000
299 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_NS16550_COM1 + 8)
300 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_NS16550_COM1 + 16)
301 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_NS16550_COM1 + 24)
304 * Low Level Configuration Settings
305 * (address mappings, register initial values, etc.)
306 * You should know what you are doing if you make changes here.
309 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
310 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
312 #define CONFIG_SYS_DLL_EXTEND 0x00
313 #define CONFIG_SYS_PCI_HOLD_DEL 0x20
315 #define CONFIG_SYS_ROMNAL 15 /* rom/flash next access time */
316 #define CONFIG_SYS_ROMFAL 31 /* rom/flash access time */
318 #define CONFIG_SYS_REFINT 430 /* # of clocks between CBR refresh cycles */
320 #define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
322 /* the following are for SDRAM only*/
323 #define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
324 #define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
325 #define CONFIG_SYS_RDLAT 4 /* data latency from read command */
326 #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
327 #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
328 #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
329 #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
330 #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
332 #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
335 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
336 #define CONFIG_SYS_EXTROM 1
337 #define CONFIG_SYS_REGDIMM 0
340 /* memory bank settings*/
342 * only bits 20-29 are actually used from these vales to set the
343 * start/end address the upper two bits will be 0, and the lower 20
344 * bits will be set to 0x00000 for a start address, or 0xfffff for an
347 #define CONFIG_SYS_BANK0_START 0x00000000
348 #define CONFIG_SYS_BANK0_END (0x4000000 - 1)
349 #define CONFIG_SYS_BANK0_ENABLE 1
350 #define CONFIG_SYS_BANK1_START 0x04000000
351 #define CONFIG_SYS_BANK1_END (0x8000000 - 1)
352 #define CONFIG_SYS_BANK1_ENABLE 1
353 #define CONFIG_SYS_BANK2_START 0x3ff00000
354 #define CONFIG_SYS_BANK2_END 0x3fffffff
355 #define CONFIG_SYS_BANK2_ENABLE 0
356 #define CONFIG_SYS_BANK3_START 0x3ff00000
357 #define CONFIG_SYS_BANK3_END 0x3fffffff
358 #define CONFIG_SYS_BANK3_ENABLE 0
359 #define CONFIG_SYS_BANK4_START 0x00000000
360 #define CONFIG_SYS_BANK4_END 0x00000000
361 #define CONFIG_SYS_BANK4_ENABLE 0
362 #define CONFIG_SYS_BANK5_START 0x00000000
363 #define CONFIG_SYS_BANK5_END 0x00000000
364 #define CONFIG_SYS_BANK5_ENABLE 0
365 #define CONFIG_SYS_BANK6_START 0x00000000
366 #define CONFIG_SYS_BANK6_END 0x00000000
367 #define CONFIG_SYS_BANK6_ENABLE 0
368 #define CONFIG_SYS_BANK7_START 0x00000000
369 #define CONFIG_SYS_BANK7_END 0x00000000
370 #define CONFIG_SYS_BANK7_ENABLE 0
372 * Memory bank enable bitmask, specifying which of the banks defined above
373 are actually present. MSB is for bank #7, LSB is for bank #0.
375 #define CONFIG_SYS_BANK_ENABLE 0x01
377 #define CONFIG_SYS_ODCR 0x75 /* configures line driver impedances, */
378 /* see 8240 book for bit definitions */
379 #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
380 /* currently accessed page in memory */
381 /* see 8240 book for details */
383 /* SDRAM 0 - 256MB */
384 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
385 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
387 /* stack in DCACHE @ 1GB (no backing mem) */
388 #if defined(USE_DINK32)
389 #define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
390 #define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
392 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
393 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
397 #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
398 #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
400 /* Flash, config addrs, etc */
401 #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
402 #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
404 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
405 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
406 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
407 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
408 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
409 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
410 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
411 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
414 * For booting Linux, the board info and command line data
415 * have to be in the first 8 MB of memory, since this is
416 * the maximum mapped by the Linux kernel during initialization.
418 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
419 /*-----------------------------------------------------------------------
422 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
423 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
425 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
426 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
428 /*-----------------------------------------------------------------------
429 * Cache Configuration
431 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
432 #if defined(CONFIG_CMD_KGDB)
433 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
436 /* values according to the manual */
438 #define CONFIG_DRAM_50MHZ 1
439 #define CONFIG_SDRAM_50MHZ
441 #define CONFIG_DISK_SPINUP_TIME 1000000
443 #endif /* __CONFIG_H */