2 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _CONFIG_DB_88F6720_H
8 #define _CONFIG_DB_88F6720_H
11 * High Level Configuration Options (easy to change)
13 #define CONFIG_DISPLAY_BOARDINFO_LATE
16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17 * for DDR ECC byte filling in the SPL before loading the main
20 #define CONFIG_SYS_TEXT_BASE 0x00800000
21 #define CONFIG_SYS_TCLK 200000000 /* 200MHz */
24 * Commands configuration
26 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
27 #define CONFIG_CMD_CACHE
28 #define CONFIG_CMD_DHCP
29 #define CONFIG_CMD_ENV
30 #define CONFIG_CMD_EXT2
31 #define CONFIG_CMD_EXT4
32 #define CONFIG_CMD_FAT
33 #define CONFIG_CMD_FS_GENERIC
34 #define CONFIG_CMD_I2C
35 #define CONFIG_CMD_PING
37 #define CONFIG_CMD_SPI
38 #define CONFIG_CMD_TFTPPUT
39 #define CONFIG_CMD_TIME
42 #define CONFIG_SYS_I2C
43 #define CONFIG_SYS_I2C_MVTWSI
44 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
45 #define CONFIG_SYS_I2C_SLAVE 0x0
46 #define CONFIG_SYS_I2C_SPEED 100000
48 /* USB/EHCI configuration */
49 #define CONFIG_EHCI_IS_TDI
50 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
52 /* SPI NOR flash default params, used by sf commands */
53 #define CONFIG_SF_DEFAULT_SPEED 1000000
54 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
56 /* Environment in SPI NOR flash */
57 #define CONFIG_ENV_IS_IN_SPI_FLASH
58 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
59 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
60 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
62 #define CONFIG_PHY_MARVELL /* there is a marvell phy */
63 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
65 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
66 #define CONFIG_SYS_ALT_MEMTEST
68 /* Additional FS support/configuration */
69 #define CONFIG_SUPPORT_VFAT
72 * mv-common.h should be defined after CMD configs since it used them
73 * to enable certain macros
75 #include "mv-common.h"
78 * Memory layout while starting into the bin_hdr via the
81 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
82 * 0x4000.4030 bin_hdr start address
83 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
84 * 0x4007.fffc BootROM stack top
86 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
87 * L2 cache thus cannot be used.
92 #define CONFIG_SPL_FRAMEWORK
93 #define CONFIG_SPL_TEXT_BASE 0x40004030
94 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
96 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
97 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
99 #ifdef CONFIG_SPL_BUILD
100 #define CONFIG_SYS_MALLOC_SIMPLE
103 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
104 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
106 #define CONFIG_SPL_LIBCOMMON_SUPPORT
107 #define CONFIG_SPL_LIBGENERIC_SUPPORT
108 #define CONFIG_SPL_SERIAL_SUPPORT
109 #define CONFIG_SPL_I2C_SUPPORT
111 /* SPL related SPI defines */
112 #define CONFIG_SPL_SPI_SUPPORT
113 #define CONFIG_SPL_SPI_FLASH_SUPPORT
114 #define CONFIG_SPL_SPI_LOAD
115 #define CONFIG_SPL_SPI_BUS 0
116 #define CONFIG_SPL_SPI_CS 0
117 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
118 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
120 #endif /* _CONFIG_DB_88F6720_H */