ebfdd1c7a3728abd54a86650fefb072da2846db2
[oweals/u-boot.git] / include / configs / da850evm.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4  *
5  * Based on davinci_dvevm.h. Original Copyrights follow:
6  *
7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8  */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 /*
14  * Board
15  */
16 #define CONFIG_DRIVER_TI_EMAC
17 /* check if direct NOR boot config is used */
18 #ifndef CONFIG_DIRECT_NOR_BOOT
19 #define CONFIG_USE_SPIFLASH
20 #endif
21
22 /*
23 * Disable DM_* for SPL build and can be re-enabled after adding
24 * DM support in SPL
25 */
26 #ifdef CONFIG_SPL_BUILD
27 #undef CONFIG_DM_SPI
28 #undef CONFIG_DM_SPI_FLASH
29 #undef CONFIG_DM_I2C
30 #undef CONFIG_DM_I2C_COMPAT
31 #endif
32 /*
33  * SoC Configuration
34  */
35 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
36 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
37 #define CONFIG_SYS_OSCIN_FREQ           24000000
38 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
39 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
40
41 #ifdef CONFIG_DIRECT_NOR_BOOT
42 #define CONFIG_ARCH_CPU_INIT
43 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
44 #endif
45
46 /*
47  * Memory Info
48  */
49 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
50 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
51 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
52 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
53
54 /* memtest start addr */
55 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
56
57 /* memtest will be run on 16MB */
58 #define CONFIG_SYS_MEMTEST_END  (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
59
60 #define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
61
62 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
63         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
64         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
65         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
66         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
67         DAVINCI_SYSCFG_SUSPSRC_I2C)
68
69 /*
70  * PLL configuration
71  */
72
73 #define CONFIG_SYS_DA850_PLL0_PLLM     24
74 #define CONFIG_SYS_DA850_PLL1_PLLM     21
75
76 /*
77  * DDR2 memory configuration
78  */
79 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
80                                         DV_DDR_PHY_EXT_STRBEN | \
81                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
82
83 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
84         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
85         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
86         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
87         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
88         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
89         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
90         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
91
92 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
93 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
94
95 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
96         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
97         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
98         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
99         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
100         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
101         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
102         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
103         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
104
105 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
106         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
107         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
108         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
109         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
110         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
111         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
112         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
113
114 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
115 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
116
117 /*
118  * Serial Driver info
119  */
120
121 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT)
122 #define CONFIG_SYS_NS16550_SERIAL
123 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
124 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
125 #endif
126 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
127
128 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
129 #ifdef CONFIG_SPL_BUILD
130 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
131 #define CONFIG_SF_DEFAULT_SPEED         30000000
132 #define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED
133 #endif
134
135 #ifdef CONFIG_USE_SPIFLASH
136 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x8000
137 #define CONFIG_SYS_SPI_U_BOOT_SIZE      0x40000
138 #endif
139
140 /*
141  * I2C Configuration
142  */
143 #ifndef CONFIG_SPL_BUILD
144 #define CONFIG_SYS_I2C_DAVINCI
145 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
146 #endif
147
148 /*
149  * Flash & Environment
150  */
151 #ifdef CONFIG_USE_NAND
152 #define CONFIG_NAND_DAVINCI
153 #define CONFIG_ENV_OFFSET               0x0 /* Block 0--not used by bootcode */
154 #define CONFIG_ENV_SIZE                 (128 << 10)
155 #define CONFIG_SYS_NAND_USE_FLASH_BBT
156 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
157 #define CONFIG_SYS_NAND_PAGE_2K
158 #define CONFIG_SYS_NAND_CS              3
159 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
160 #define CONFIG_SYS_NAND_MASK_CLE                0x10
161 #define CONFIG_SYS_NAND_MASK_ALE                0x8
162 #undef CONFIG_SYS_NAND_HW_ECC
163 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
164 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
165 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
166 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)
167 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
168 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x28000
169 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x60000
170 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
171 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
172 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
173                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
174                                         CONFIG_SYS_MALLOC_LEN -       \
175                                         GENERATED_GBL_DATA_SIZE)
176 #define CONFIG_SYS_NAND_ECCPOS          {                               \
177                                 24, 25, 26, 27, 28, \
178                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
179                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
180                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
181                                 59, 60, 61, 62, 63 }
182 #define CONFIG_SYS_NAND_PAGE_COUNT      64
183 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
184 #define CONFIG_SYS_NAND_ECCSIZE         512
185 #define CONFIG_SYS_NAND_ECCBYTES        10
186 #define CONFIG_SYS_NAND_OOBSIZE         64
187 #define CONFIG_SPL_NAND_BASE
188 #define CONFIG_SPL_NAND_DRIVERS
189 #define CONFIG_SPL_NAND_ECC
190 #define CONFIG_SPL_NAND_LOAD
191 #endif
192
193 /*
194  * Network & Ethernet Configuration
195  */
196 #ifdef CONFIG_DRIVER_TI_EMAC
197 #define CONFIG_MII
198 #define CONFIG_BOOTP_DNS2
199 #define CONFIG_BOOTP_SEND_HOSTNAME
200 #define CONFIG_NET_RETRY_COUNT  10
201 #endif
202
203 #ifdef CONFIG_USE_NOR
204 #define CONFIG_FLASH_CFI_DRIVER
205 #define CONFIG_SYS_FLASH_CFI
206 #define CONFIG_SYS_FLASH_PROTECTION
207 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* max number of flash banks */
208 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
209 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_FLASH_SECT_SZ * 3)
210 #define CONFIG_ENV_SIZE                 (10 << 10) /* 10KB */
211 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
212 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
213 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
214                + 3)
215 #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SZ
216 #endif
217
218 #ifdef CONFIG_USE_SPIFLASH
219 #define CONFIG_ENV_SIZE                 (64 << 10)
220 #define CONFIG_ENV_OFFSET               (512 << 10)
221 #define CONFIG_ENV_SECT_SIZE            (64 << 10)
222 #ifdef CONFIG_SPL_BUILD
223 #undef CONFIG_SPI_FLASH_MTD
224 #endif
225 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
226 #define CONFIG_MTD_PARTITIONS           /* required for UBI partition support */
227 #endif
228
229 #define CONFIG_DA8XX_GPIO
230 /*
231  * U-Boot general configuration
232  */
233 #define CONFIG_MISC_INIT_R
234 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
235 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
236 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
237 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
238 #define CONFIG_MX_CYCLIC
239
240 /*
241  * Linux Information
242  */
243 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
244 #define CONFIG_HWCONFIG         /* enable hwconfig */
245 #define CONFIG_CMDLINE_TAG
246 #define CONFIG_REVISION_TAG
247 #define CONFIG_SETUP_MEMORY_TAGS
248
249 #define CONFIG_BOOTCOMMAND \
250                 "run envboot; " \
251                 "run mmcboot; "
252
253 #define DEFAULT_LINUX_BOOT_ENV \
254         "loadaddr=0xc0700000\0" \
255         "fdtaddr=0xc0600000\0" \
256         "scriptaddr=0xc0600000\0"
257
258 #include <environment/ti/mmc.h>
259
260 #define CONFIG_EXTRA_ENV_SETTINGS \
261         DEFAULT_LINUX_BOOT_ENV \
262         DEFAULT_MMC_TI_ARGS \
263         "bootpart=0:2\0" \
264         "bootdir=/boot\0" \
265         "bootfile=zImage\0" \
266         "fdtfile=da850-evm.dtb\0" \
267         "boot_fdt=yes\0" \
268         "boot_fit=0\0" \
269         "console=ttyS2,115200n8\0" \
270         "hwconfig=dsp:wake=yes"
271
272 #ifdef CONFIG_CMD_BDI
273 #define CONFIG_CLOCKS
274 #endif
275
276 #ifdef CONFIG_USE_NAND
277 #define CONFIG_MTD_DEVICE
278 #define CONFIG_MTD_PARTITIONS
279 #endif
280
281 #if !defined(CONFIG_USE_NAND) && \
282         !defined(CONFIG_USE_NOR) && \
283         !defined(CONFIG_USE_SPIFLASH)
284 #define CONFIG_ENV_SIZE         (16 << 10)
285 #endif
286
287 #ifndef CONFIG_DIRECT_NOR_BOOT
288 /* defines for SPL */
289 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
290                                                 CONFIG_SYS_MALLOC_LEN)
291 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
292 #define CONFIG_SPL_STACK        0x8001ff00
293 #define CONFIG_SPL_TEXT_BASE    0x80000000
294 #define CONFIG_SPL_MAX_FOOTPRINT        32768
295 #define CONFIG_SPL_PAD_TO       32768
296 #endif
297
298 /* Load U-Boot Image From MMC */
299
300 /* additions for new relocation code, must added to all boards */
301 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
302
303 #ifdef CONFIG_DIRECT_NOR_BOOT
304 #define CONFIG_SYS_INIT_SP_ADDR         0x8001ff00
305 #else
306 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
307                                         GENERATED_GBL_DATA_SIZE)
308 #endif /* CONFIG_DIRECT_NOR_BOOT */
309
310 #include <asm/arch/hardware.h>
311
312 #endif /* __CONFIG_H */