1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Based on davinci_dvevm.h. Original Copyrights follow:
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
16 /* check if direct NOR boot config is used */
17 #ifndef CONFIG_DIRECT_NOR_BOOT
18 #define CONFIG_USE_SPIFLASH
22 * Disable DM_* for SPL build and can be re-enabled after adding
25 #ifdef CONFIG_SPL_BUILD
27 #undef CONFIG_DM_I2C_COMPAT
32 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
33 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
34 #define CONFIG_SYS_OSCIN_FREQ 24000000
35 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
36 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
37 #define CONFIG_SKIP_LOWLEVEL_INIT
39 #ifdef CONFIG_DIRECT_NOR_BOOT
40 #define CONFIG_ARCH_CPU_INIT
41 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
47 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
48 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
49 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
50 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
52 /* memtest start addr */
53 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
55 /* memtest will be run on 16MB */
56 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
58 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
59 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
60 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
61 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
62 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
63 DAVINCI_SYSCFG_SUSPSRC_I2C)
69 #define CONFIG_SYS_DA850_PLL0_PLLM 24
70 #define CONFIG_SYS_DA850_PLL1_PLLM 21
73 * DDR2 memory configuration
75 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
76 DV_DDR_PHY_EXT_STRBEN | \
77 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
79 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
80 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
81 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
82 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
83 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
84 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
85 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
86 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
88 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
89 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
91 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
92 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
93 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
94 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
95 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
96 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
97 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
98 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
99 (0 << DV_DDR_SDTMR1_WTR_SHIFT))
101 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
102 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
103 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
104 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
105 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
106 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
107 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
108 (0 << DV_DDR_SDTMR2_CKE_SHIFT))
110 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
111 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
117 #if !CONFIG_IS_ENABLED(DM_SERIAL)
118 #define CONFIG_SYS_NS16550_SERIAL
119 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
121 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
123 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
124 #ifdef CONFIG_SPL_BUILD
125 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
128 #ifdef CONFIG_USE_SPIFLASH
129 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
130 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
136 #ifndef CONFIG_SPL_BUILD
137 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
141 * Flash & Environment
144 #ifdef CONFIG_ENV_IS_IN_NAND
145 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
146 #define CONFIG_ENV_SIZE (128 << 10)
147 #define CONFIG_ENV_SECT_SIZE (128 << 10)
149 #define CONFIG_SYS_NAND_USE_FLASH_BBT
150 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
151 #define CONFIG_SYS_NAND_PAGE_2K
152 #define CONFIG_SYS_NAND_CS 3
153 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
154 #define CONFIG_SYS_NAND_MASK_CLE 0x10
155 #define CONFIG_SYS_NAND_MASK_ALE 0x8
156 #undef CONFIG_SYS_NAND_HW_ECC
157 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
158 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
159 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
160 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
161 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
162 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
163 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
164 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
165 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
166 CONFIG_SYS_NAND_U_BOOT_SIZE - \
167 CONFIG_SYS_MALLOC_LEN - \
168 GENERATED_GBL_DATA_SIZE)
169 #define CONFIG_SYS_NAND_ECCPOS { \
170 24, 25, 26, 27, 28, \
171 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
172 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
173 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
175 #define CONFIG_SYS_NAND_PAGE_COUNT 64
176 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
177 #define CONFIG_SYS_NAND_ECCSIZE 512
178 #define CONFIG_SYS_NAND_ECCBYTES 10
179 #define CONFIG_SYS_NAND_OOBSIZE 64
180 #define CONFIG_SPL_NAND_BASE
181 #define CONFIG_SPL_NAND_DRIVERS
182 #define CONFIG_SPL_NAND_ECC
183 #define CONFIG_SPL_NAND_LOAD
187 * Network & Ethernet Configuration
189 #ifdef CONFIG_DRIVER_TI_EMAC
190 #define CONFIG_BOOTP_DNS2
191 #define CONFIG_BOOTP_SEND_HOSTNAME
192 #define CONFIG_NET_RETRY_COUNT 10
195 #ifdef CONFIG_USE_NOR
196 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
197 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
198 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
199 #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
200 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
201 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
202 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
204 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
207 #ifdef CONFIG_USE_SPIFLASH
208 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
209 #define CONFIG_ENV_SIZE (64 << 10)
210 #define CONFIG_ENV_OFFSET (512 << 10)
211 #define CONFIG_ENV_SECT_SIZE (64 << 10)
213 #ifdef CONFIG_SPL_BUILD
214 #undef CONFIG_SPI_FLASH_MTD
219 * U-Boot general configuration
221 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
222 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
223 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
224 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
225 #define CONFIG_MX_CYCLIC
230 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
231 #define CONFIG_HWCONFIG /* enable hwconfig */
232 #define CONFIG_CMDLINE_TAG
233 #define CONFIG_REVISION_TAG
234 #define CONFIG_SETUP_MEMORY_TAGS
236 #define CONFIG_BOOTCOMMAND \
240 #define DEFAULT_LINUX_BOOT_ENV \
241 "loadaddr=0xc0700000\0" \
242 "fdtaddr=0xc0600000\0" \
243 "scriptaddr=0xc0600000\0"
245 #include <environment/ti/mmc.h>
247 #define CONFIG_EXTRA_ENV_SETTINGS \
248 DEFAULT_LINUX_BOOT_ENV \
249 DEFAULT_MMC_TI_ARGS \
252 "bootfile=zImage\0" \
253 "fdtfile=da850-evm.dtb\0" \
256 "console=ttyS2,115200n8\0" \
257 "hwconfig=dsp:wake=yes"
259 #ifdef CONFIG_CMD_BDI
260 #define CONFIG_CLOCKS
263 #if !defined(CONFIG_NAND) && \
264 !defined(CONFIG_USE_NOR) && \
265 !defined(CONFIG_USE_SPIFLASH)
266 #define CONFIG_ENV_SIZE (16 << 10)
269 #ifndef CONFIG_DIRECT_NOR_BOOT
270 /* defines for SPL */
271 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
272 CONFIG_SYS_MALLOC_LEN)
273 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
274 #define CONFIG_SPL_STACK 0x8001ff00
275 #define CONFIG_SPL_TEXT_BASE 0x80000000
276 #define CONFIG_SPL_MAX_FOOTPRINT 32768
277 #define CONFIG_SPL_PAD_TO 32768
280 /* Load U-Boot Image From MMC */
282 /* additions for new relocation code, must added to all boards */
283 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
285 #ifdef CONFIG_DIRECT_NOR_BOOT
286 #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
288 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
289 GENERATED_GBL_DATA_SIZE)
290 #endif /* CONFIG_DIRECT_NOR_BOOT */
292 #include <asm/arch/hardware.h>
294 #endif /* __CONFIG_H */