3a42ff3dc0ee7d2b414c58d9064db5f47fd637a5
[oweals/u-boot.git] / include / configs / da850evm.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4  *
5  * Based on davinci_dvevm.h. Original Copyrights follow:
6  *
7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8  */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 /*
14  * Board
15  */
16 #define CONFIG_DRIVER_TI_EMAC
17 /* check if direct NOR boot config is used */
18 #ifndef CONFIG_DIRECT_NOR_BOOT
19 #define CONFIG_USE_SPIFLASH
20 #endif
21
22 /*
23 * Disable DM_* for SPL build and can be re-enabled after adding
24 * DM support in SPL
25 */
26 #ifdef CONFIG_SPL_BUILD
27 #undef CONFIG_DM_SPI
28 #undef CONFIG_DM_SPI_FLASH
29 #undef CONFIG_DM_I2C
30 #undef CONFIG_DM_I2C_COMPAT
31 #endif
32 /*
33  * SoC Configuration
34  */
35 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
36 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
37 #define CONFIG_SYS_OSCIN_FREQ           24000000
38 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
39 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
40
41 #ifdef CONFIG_DIRECT_NOR_BOOT
42 #define CONFIG_ARCH_CPU_INIT
43 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
44 #endif
45
46 /*
47  * Memory Info
48  */
49 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
50 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
51 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
52 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
53
54 /* memtest start addr */
55 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
56
57 /* memtest will be run on 16MB */
58 #define CONFIG_SYS_MEMTEST_END  (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
59
60 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
61         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
62         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
63         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
64         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
65         DAVINCI_SYSCFG_SUSPSRC_I2C)
66
67 /*
68  * PLL configuration
69  */
70
71 #define CONFIG_SYS_DA850_PLL0_PLLM     24
72 #define CONFIG_SYS_DA850_PLL1_PLLM     21
73
74 /*
75  * DDR2 memory configuration
76  */
77 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
78                                         DV_DDR_PHY_EXT_STRBEN | \
79                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
80
81 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
82         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
83         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
84         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
85         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
86         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
87         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
88         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
89
90 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
91 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
92
93 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
94         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
95         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
96         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
97         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
98         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
99         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
100         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
101         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
102
103 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
104         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
105         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
106         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
107         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
108         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
109         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
110         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
111
112 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
113 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
114
115 /*
116  * Serial Driver info
117  */
118
119 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT)
120 #define CONFIG_SYS_NS16550_SERIAL
121 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
122 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
123 #endif
124 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
125
126 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
127 #ifdef CONFIG_SPL_BUILD
128 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
129 #define CONFIG_SF_DEFAULT_SPEED         30000000
130 #define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED
131 #endif
132
133 #ifdef CONFIG_USE_SPIFLASH
134 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x8000
135 #define CONFIG_SYS_SPI_U_BOOT_SIZE      0x40000
136 #endif
137
138 /*
139  * I2C Configuration
140  */
141 #ifndef CONFIG_SPL_BUILD
142 #define CONFIG_SYS_I2C_DAVINCI
143 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
144 #endif
145
146 /*
147  * Flash & Environment
148  */
149 #ifdef CONFIG_NAND
150 #define CONFIG_ENV_OFFSET               0x0 /* Block 0--not used by bootcode */
151 #define CONFIG_ENV_SIZE                 (128 << 10)
152 #define CONFIG_SYS_NAND_USE_FLASH_BBT
153 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
154 #define CONFIG_SYS_NAND_PAGE_2K
155 #define CONFIG_SYS_NAND_CS              3
156 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
157 #define CONFIG_SYS_NAND_MASK_CLE                0x10
158 #define CONFIG_SYS_NAND_MASK_ALE                0x8
159 #undef CONFIG_SYS_NAND_HW_ECC
160 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
161 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
162 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
163 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)
164 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
165 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x28000
166 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x60000
167 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
168 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
169 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
170                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
171                                         CONFIG_SYS_MALLOC_LEN -       \
172                                         GENERATED_GBL_DATA_SIZE)
173 #define CONFIG_SYS_NAND_ECCPOS          {                               \
174                                 24, 25, 26, 27, 28, \
175                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
176                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
177                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
178                                 59, 60, 61, 62, 63 }
179 #define CONFIG_SYS_NAND_PAGE_COUNT      64
180 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
181 #define CONFIG_SYS_NAND_ECCSIZE         512
182 #define CONFIG_SYS_NAND_ECCBYTES        10
183 #define CONFIG_SYS_NAND_OOBSIZE         64
184 #define CONFIG_SPL_NAND_BASE
185 #define CONFIG_SPL_NAND_DRIVERS
186 #define CONFIG_SPL_NAND_ECC
187 #define CONFIG_SPL_NAND_LOAD
188 #endif
189
190 /*
191  * Network & Ethernet Configuration
192  */
193 #ifdef CONFIG_DRIVER_TI_EMAC
194 #define CONFIG_MII
195 #define CONFIG_BOOTP_DNS2
196 #define CONFIG_BOOTP_SEND_HOSTNAME
197 #define CONFIG_NET_RETRY_COUNT  10
198 #endif
199
200 #ifdef CONFIG_USE_NOR
201 #define CONFIG_FLASH_CFI_DRIVER
202 #define CONFIG_SYS_FLASH_CFI
203 #define CONFIG_SYS_FLASH_PROTECTION
204 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* max number of flash banks */
205 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
206 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_FLASH_SECT_SZ * 3)
207 #define CONFIG_ENV_SIZE                 (10 << 10) /* 10KB */
208 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
209 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
210 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
211                + 3)
212 #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SZ
213 #endif
214
215 #ifdef CONFIG_USE_SPIFLASH
216 #define CONFIG_ENV_SIZE                 (64 << 10)
217 #define CONFIG_ENV_OFFSET               (512 << 10)
218 #define CONFIG_ENV_SECT_SIZE            (64 << 10)
219 #ifdef CONFIG_SPL_BUILD
220 #undef CONFIG_SPI_FLASH_MTD
221 #endif
222 #endif
223
224 /*
225  * U-Boot general configuration
226  */
227 #define CONFIG_MISC_INIT_R
228 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
229 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
230 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
231 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
232 #define CONFIG_MX_CYCLIC
233
234 /*
235  * Linux Information
236  */
237 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
238 #define CONFIG_HWCONFIG         /* enable hwconfig */
239 #define CONFIG_CMDLINE_TAG
240 #define CONFIG_REVISION_TAG
241 #define CONFIG_SETUP_MEMORY_TAGS
242
243 #define CONFIG_BOOTCOMMAND \
244                 "run envboot; " \
245                 "run mmcboot; "
246
247 #define DEFAULT_LINUX_BOOT_ENV \
248         "loadaddr=0xc0700000\0" \
249         "fdtaddr=0xc0600000\0" \
250         "scriptaddr=0xc0600000\0"
251
252 #include <environment/ti/mmc.h>
253
254 #define CONFIG_EXTRA_ENV_SETTINGS \
255         DEFAULT_LINUX_BOOT_ENV \
256         DEFAULT_MMC_TI_ARGS \
257         "bootpart=0:2\0" \
258         "bootdir=/boot\0" \
259         "bootfile=zImage\0" \
260         "fdtfile=da850-evm.dtb\0" \
261         "boot_fdt=yes\0" \
262         "boot_fit=0\0" \
263         "console=ttyS2,115200n8\0" \
264         "hwconfig=dsp:wake=yes"
265
266 #ifdef CONFIG_CMD_BDI
267 #define CONFIG_CLOCKS
268 #endif
269
270 #if !defined(CONFIG_NAND) && \
271         !defined(CONFIG_USE_NOR) && \
272         !defined(CONFIG_USE_SPIFLASH)
273 #define CONFIG_ENV_SIZE         (16 << 10)
274 #endif
275
276 #ifndef CONFIG_DIRECT_NOR_BOOT
277 /* defines for SPL */
278 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
279                                                 CONFIG_SYS_MALLOC_LEN)
280 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
281 #define CONFIG_SPL_STACK        0x8001ff00
282 #define CONFIG_SPL_TEXT_BASE    0x80000000
283 #define CONFIG_SPL_MAX_FOOTPRINT        32768
284 #define CONFIG_SPL_PAD_TO       32768
285 #endif
286
287 /* Load U-Boot Image From MMC */
288
289 /* additions for new relocation code, must added to all boards */
290 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
291
292 #ifdef CONFIG_DIRECT_NOR_BOOT
293 #define CONFIG_SYS_INIT_SP_ADDR         0x8001ff00
294 #else
295 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
296                                         GENERATED_GBL_DATA_SIZE)
297 #endif /* CONFIG_DIRECT_NOR_BOOT */
298
299 #include <asm/arch/hardware.h>
300
301 #endif /* __CONFIG_H */