2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 * Based on davinci_dvevm.h. Original Copyrights follow:
6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 #define CONFIG_DRIVER_TI_EMAC
30 #define CONFIG_USE_SPIFLASH
36 #define CONFIG_MACH_DAVINCI_DA850_EVM
37 #define CONFIG_ARM926EJS /* arm926ejs CPU core */
38 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
39 #define CONFIG_SOC_DA850 /* TI DA850 SoC */
40 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
41 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
42 #define CONFIG_SYS_OSCIN_FREQ 24000000
43 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
44 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
45 #define CONFIG_SYS_HZ 1000
46 #define CONFIG_SYS_TEXT_BASE 0xc1080000
47 #define CONFIG_SYS_DA850_PLL_INIT
48 #define CONFIG_SYS_DA850_DDR_INIT
53 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
54 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
55 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
56 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
58 /* memtest start addr */
59 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
61 /* memtest will be run on 16MB */
62 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
64 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
65 #define CONFIG_STACKSIZE (256*1024) /* regular stack */
67 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
68 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
69 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
70 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
71 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
72 DAVINCI_SYSCFG_SUSPSRC_I2C)
77 #define CONFIG_SYS_DV_CLKMODE 0
78 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1
79 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
80 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
81 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
82 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
83 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
84 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
85 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
87 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1
88 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
89 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
90 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
92 #define CONFIG_SYS_DA850_PLL0_PLLM 24
93 #define CONFIG_SYS_DA850_PLL1_PLLM 21
96 * DDR2 memory configuration
98 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
99 DV_DDR_PHY_EXT_STRBEN | \
100 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
102 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
103 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
104 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
105 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
106 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
107 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
108 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
109 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
111 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
112 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
114 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
115 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
116 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
117 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
118 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
119 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
120 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
121 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
122 (0 << DV_DDR_SDTMR1_WTR_SHIFT))
124 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
125 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
126 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
127 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
128 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
129 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
130 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
131 (0 << DV_DDR_SDTMR2_CKE_SHIFT))
133 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
134 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
139 #define CONFIG_SYS_NS16550
140 #define CONFIG_SYS_NS16550_SERIAL
141 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
142 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
143 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
144 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
145 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
148 #define CONFIG_SPI_FLASH
149 #define CONFIG_SPI_FLASH_STMICRO
150 #define CONFIG_SPI_FLASH_WINBOND
151 #define CONFIG_DAVINCI_SPI
152 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
153 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
154 #define CONFIG_SF_DEFAULT_SPEED 30000000
155 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
157 #ifdef CONFIG_USE_SPIFLASH
158 #define CONFIG_SPL_SPI_SUPPORT
159 #define CONFIG_SPL_SPI_FLASH_SUPPORT
160 #define CONFIG_SPL_SPI_LOAD
161 #define CONFIG_SPL_SPI_BUS 0
162 #define CONFIG_SPL_SPI_CS 0
163 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
164 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
170 #define CONFIG_HARD_I2C
171 #define CONFIG_DRIVER_DAVINCI_I2C
172 #define CONFIG_SYS_I2C_SPEED 25000
173 #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
174 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
177 * Flash & Environment
179 #ifdef CONFIG_USE_NAND
180 #undef CONFIG_ENV_IS_IN_FLASH
181 #define CONFIG_NAND_DAVINCI
182 #define CONFIG_SYS_NO_FLASH
183 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
184 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
185 #define CONFIG_ENV_SIZE (128 << 10)
186 #define CONFIG_SYS_NAND_USE_FLASH_BBT
187 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
188 #define CONFIG_SYS_NAND_PAGE_2K
189 #define CONFIG_SYS_NAND_CS 3
190 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
191 #define CONFIG_SYS_CLE_MASK 0x10
192 #define CONFIG_SYS_ALE_MASK 0x8
193 #undef CONFIG_SYS_NAND_HW_ECC
194 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
198 * Network & Ethernet Configuration
200 #ifdef CONFIG_DRIVER_TI_EMAC
202 #define CONFIG_BOOTP_DEFAULT
203 #define CONFIG_BOOTP_DNS
204 #define CONFIG_BOOTP_DNS2
205 #define CONFIG_BOOTP_SEND_HOSTNAME
206 #define CONFIG_NET_RETRY_COUNT 10
209 #ifdef CONFIG_USE_NOR
210 #define CONFIG_ENV_IS_IN_FLASH
211 #define CONFIG_FLASH_CFI_DRIVER
212 #define CONFIG_SYS_FLASH_CFI
213 #define CONFIG_SYS_FLASH_PROTECTION
214 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
215 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
216 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
217 #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
218 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
219 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
220 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
222 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
225 #ifdef CONFIG_USE_SPIFLASH
226 #undef CONFIG_ENV_IS_IN_FLASH
227 #undef CONFIG_ENV_IS_IN_NAND
228 #define CONFIG_ENV_IS_IN_SPI_FLASH
229 #define CONFIG_ENV_SIZE (64 << 10)
230 #define CONFIG_ENV_OFFSET (256 << 10)
231 #define CONFIG_ENV_SECT_SIZE (64 << 10)
232 #define CONFIG_SYS_NO_FLASH
236 * U-Boot general configuration
238 #define CONFIG_MISC_INIT_R
239 #define CONFIG_BOARD_EARLY_INIT_F
240 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
241 #define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */
242 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
243 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
244 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
245 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
246 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
247 #define CONFIG_VERSION_VARIABLE
248 #define CONFIG_AUTO_COMPLETE
249 #define CONFIG_SYS_HUSH_PARSER
250 #define CONFIG_CMDLINE_EDITING
251 #define CONFIG_SYS_LONGHELP
252 #define CONFIG_CRC32_VERIFY
253 #define CONFIG_MX_CYCLIC
258 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
259 #define CONFIG_HWCONFIG /* enable hwconfig */
260 #define CONFIG_CMDLINE_TAG
261 #define CONFIG_REVISION_TAG
262 #define CONFIG_SETUP_MEMORY_TAGS
263 #define CONFIG_BOOTARGS \
264 "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
265 #define CONFIG_BOOTDELAY 3
266 #define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes"
271 #include <config_cmd_default.h>
272 #define CONFIG_CMD_ENV
273 #define CONFIG_CMD_ASKENV
274 #define CONFIG_CMD_DHCP
275 #define CONFIG_CMD_DIAG
276 #define CONFIG_CMD_MII
277 #define CONFIG_CMD_PING
278 #define CONFIG_CMD_SAVES
279 #define CONFIG_CMD_MEMORY
281 #ifdef CONFIG_CMD_BDI
282 #define CONFIG_CLOCKS
285 #ifndef CONFIG_DRIVER_TI_EMAC
286 #undef CONFIG_CMD_NET
287 #undef CONFIG_CMD_DHCP
288 #undef CONFIG_CMD_MII
289 #undef CONFIG_CMD_PING
292 #ifdef CONFIG_USE_NAND
293 #undef CONFIG_CMD_FLASH
294 #undef CONFIG_CMD_IMLS
295 #define CONFIG_CMD_NAND
297 #define CONFIG_CMD_MTDPARTS
298 #define CONFIG_MTD_DEVICE
299 #define CONFIG_MTD_PARTITIONS
301 #define CONFIG_RBTREE
302 #define CONFIG_CMD_UBI
303 #define CONFIG_CMD_UBIFS
306 #ifdef CONFIG_USE_SPIFLASH
307 #undef CONFIG_CMD_IMLS
308 #undef CONFIG_CMD_FLASH
309 #define CONFIG_CMD_SPI
310 #define CONFIG_CMD_SF
311 #define CONFIG_CMD_SAVEENV
314 #if !defined(CONFIG_USE_NAND) && \
315 !defined(CONFIG_USE_NOR) && \
316 !defined(CONFIG_USE_SPIFLASH)
317 #define CONFIG_ENV_IS_NOWHERE
318 #define CONFIG_SYS_NO_FLASH
319 #define CONFIG_ENV_SIZE (16 << 10)
320 #undef CONFIG_CMD_IMLS
321 #undef CONFIG_CMD_ENV
324 /* SD/MMC configuration */
325 #ifndef CONFIG_USE_NOR
327 #define CONFIG_DAVINCI_MMC_SD1
328 #define CONFIG_GENERIC_MMC
329 #define CONFIG_DAVINCI_MMC
333 * Enable MMC commands only when
334 * MMC support is present
337 #define CONFIG_DOS_PARTITION
338 #define CONFIG_CMD_EXT2
339 #define CONFIG_CMD_FAT
340 #define CONFIG_CMD_MMC
343 /* defines for SPL */
345 #define CONFIG_SPL_SERIAL_SUPPORT
346 #define CONFIG_SPL_LIBCOMMON_SUPPORT
347 #define CONFIG_SPL_LIBGENERIC_SUPPORT
348 #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
349 #define CONFIG_SPL_STACK 0x8001ff00
350 #define CONFIG_SPL_TEXT_BASE 0x80000000
351 #define CONFIG_SPL_MAX_SIZE 32768
353 /* additions for new relocation code, must added to all boards */
354 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
355 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
356 GENERATED_GBL_DATA_SIZE)
357 #endif /* __CONFIG_H */