3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * High Level Configuration Options
35 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
36 #define CONFIG_HHP_CRADLE 1 /* on an Cradle Board */
38 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
41 * Size of malloc() pool
43 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
44 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
49 #define CONFIG_DRIVER_SMC91111
50 #define CONFIG_SMC91111_BASE 0x10000300
51 #define CONFIG_SMC91111_EXT_PHY
52 #define CONFIG_SMC_USE_32_BIT
55 * select serial console configuration
57 #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
59 /* allow to overwrite serial and ethaddr */
60 #define CONFIG_ENV_OVERWRITE
62 #define CONFIG_BAUDRATE 115200
64 #define CONFIG_COMMANDS (CONFIG_CMD_DFL)
66 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
67 #include <cmd_confdefs.h>
69 #define CONFIG_BOOTDELAY 3
70 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200"
71 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
72 #define CONFIG_NETMASK 255.255.0.0
73 #define CONFIG_IPADDR 192.168.0.21
74 #define CONFIG_SERVERIP 192.168.0.250
75 #define CONFIG_BOOTCOMMAND "bootm 40000"
76 #define CONFIG_CMDLINE_TAG
79 * Miscellaneous configurable options
81 #define CFG_LONGHELP /* undef to save memory */
82 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
83 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
84 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
85 #define CFG_MAXARGS 16 /* max number of command args */
86 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
88 #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
89 #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
91 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
93 #define CFG_LOAD_ADDR 0xa2000000 /* default load address */
95 #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
96 #define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
99 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
104 * The stack sizes are set up in start.S using the settings below
106 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
107 #ifdef CONFIG_USE_IRQ
108 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
109 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
113 * Physical Memory Map
115 #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
116 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
117 #define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */
118 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
119 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
120 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
121 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
122 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
123 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
125 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
126 #define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
127 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
129 #define CFG_DRAM_BASE 0xa0000000
130 #define CFG_DRAM_SIZE 0x04000000
132 #define CFG_FLASH_BASE PHYS_FLASH_1
135 * FLASH and environment organization
137 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
138 #define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
140 /* timeout values are in ticks */
141 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
142 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
144 #define CFG_ENV_IS_IN_FLASH 1
145 #define CFG_ENV_ADDR 0x00020000 /* absolute address for now */
146 #define CFG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */
148 /******************************************************************************
150 * CPU specific defines
152 ******************************************************************************/
157 * GPIO pin assignments
158 * GPIO Name Dir Out AF
181 * 22 PGMEN O 1 FIXME for debug only enable flash
201 * 42 RS232FOFF O 0 00
241 * NOTE: All NC's are defined to be outputs
244 /* Pin direction control */
245 /* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */
246 #define CFG_GPDR0_VAL 0xfff3bf02
247 #define CFG_GPDR1_VAL 0xfbffbf83
248 #define CFG_GPDR2_VAL 0x0001ffff
249 /* Set and Clear registers */
250 #define CFG_GPSR0_VAL 0x00400800
251 #define CFG_GPSR1_VAL 0x00000480
252 #define CFG_GPSR2_VAL 0x00014000
253 #define CFG_GPCR0_VAL 0x00000000
254 #define CFG_GPCR1_VAL 0x00000000
255 #define CFG_GPCR2_VAL 0x00000000
256 /* Edge detect registers (these are set by the kernel) */
257 #define CFG_GRER0_VAL 0x00000000
258 #define CFG_GRER1_VAL 0x00000000
259 #define CFG_GRER2_VAL 0x00000000
260 #define CFG_GFER0_VAL 0x00000000
261 #define CFG_GFER1_VAL 0x00000000
262 #define CFG_GFER2_VAL 0x00000000
263 /* Alternate function registers */
264 #define CFG_GAFR0_L_VAL 0x00000000
265 #define CFG_GAFR0_U_VAL 0x00000010
266 #define CFG_GAFR1_L_VAL 0x900a9550
267 #define CFG_GAFR1_U_VAL 0x00000008
268 #define CFG_GAFR2_L_VAL 0x20000000
269 #define CFG_GAFR2_U_VAL 0x00000002
272 * Clocks, power control and interrupts
274 #define CFG_PSSR_VAL 0x00000020
275 #define CFG_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
276 #define CFG_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
277 #define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
289 * FIXME Can ethernet be burst read and/or write?? This is set for lubbock
290 * Verify timings on all
292 #define CFG_MSC0_VAL 0x000023FA /* flash bank (cs0) */
293 /*#define CFG_MSC1_VAL 0x00003549 / * SuperIO bank (cs2) */
294 #define CFG_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */
295 #define CFG_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */
297 #define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */
298 #define CFG_MDMRS_VAL 0x00000000
299 #define CFG_MDREFR_VAL 0x00018018
301 #define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */
302 #define CFG_MDMRS_VAL 0x00000000
303 #define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */
307 * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
309 #define CFG_MECR_VAL 0x00000000
310 #define CFG_MCMEM0_VAL 0x00010504
311 #define CFG_MCMEM1_VAL 0x00010504
312 #define CFG_MCATT0_VAL 0x00010504
313 #define CFG_MCATT1_VAL 0x00010504
314 #define CFG_MCIO0_VAL 0x00004715
315 #define CFG_MCIO1_VAL 0x00004715
317 /* Board specific defines */
328 #define CRADLE_LED_SET_REG GPSR2
329 #define CRADLE_LED_CLR_REG GPCR2
331 /* SuperIO defines */
332 #define CRADLE_SIO_INDEX 0x2e
333 #define CRADLE_SIO_DATA 0x2f
336 #define CRADLE_CPLD_PHYS 0x08000000
337 #define CRADLE_SIO1_PHYS 0x08100000
338 #define CRADLE_SIO2_PHYS 0x08200000
339 #define CRADLE_SIO3_PHYS 0x08300000
340 #define CRADLE_ETH_PHYS 0x10000000
344 /* global prototypes */
345 void led_code(int code, int color);
349 #endif /* __CONFIG_H */