2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * Corenet DS style board configuration file
29 #include "../board/freescale/common/ics307_clk.h"
31 #ifdef CONFIG_RAMBOOT_PBL
32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
36 /* High Level Configuration Options */
38 #define CONFIG_E500 /* BOOKE e500 family */
39 #define CONFIG_E500MC /* BOOKE e500mc family */
40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
41 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
42 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
43 #define CONFIG_MP /* support multiple processors */
45 #ifndef CONFIG_SYS_TEXT_BASE
46 #define CONFIG_SYS_TEXT_BASE 0xeff80000
49 #ifndef CONFIG_RESET_VECTOR_ADDRESS
50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
54 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
55 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
56 #define CONFIG_PCI /* Enable PCI/PCIE */
57 #define CONFIG_PCIE1 /* PCIE controler 1 */
58 #define CONFIG_PCIE2 /* PCIE controler 2 */
59 #define CONFIG_PCIE3 /* PCIE controler 3 */
60 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
61 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
63 #define CONFIG_SYS_SRIO
64 #define CONFIG_SRIO1 /* SRIO port 1 */
65 #define CONFIG_SRIO2 /* SRIO port 2 */
67 #define CONFIG_FSL_LAW /* Use common FSL init code */
69 #define CONFIG_ENV_OVERWRITE
71 #ifdef CONFIG_SYS_NO_FLASH
72 #define CONFIG_ENV_IS_NOWHERE
74 #define CONFIG_FLASH_CFI_DRIVER
75 #define CONFIG_SYS_FLASH_CFI
76 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
79 #if defined(CONFIG_SPIFLASH)
80 #define CONFIG_SYS_EXTRA_ENV_RELOC
81 #define CONFIG_ENV_IS_IN_SPI_FLASH
82 #define CONFIG_ENV_SPI_BUS 0
83 #define CONFIG_ENV_SPI_CS 0
84 #define CONFIG_ENV_SPI_MAX_HZ 10000000
85 #define CONFIG_ENV_SPI_MODE 0
86 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
87 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
88 #define CONFIG_ENV_SECT_SIZE 0x10000
89 #elif defined(CONFIG_SDCARD)
90 #define CONFIG_SYS_EXTRA_ENV_RELOC
91 #define CONFIG_ENV_IS_IN_MMC
92 #define CONFIG_SYS_MMC_ENV_DEV 0
93 #define CONFIG_ENV_SIZE 0x2000
94 #define CONFIG_ENV_OFFSET (512 * 1097)
95 #elif defined(CONFIG_NAND)
96 #define CONFIG_SYS_EXTRA_ENV_RELOC
97 #define CONFIG_ENV_IS_IN_NAND
98 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
99 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
101 #define CONFIG_ENV_IS_IN_FLASH
102 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
103 #define CONFIG_ENV_SIZE 0x2000
104 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
107 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
110 * These can be toggled for performance analysis, otherwise use default.
112 #define CONFIG_SYS_CACHE_STASHING
113 #define CONFIG_BACKSIDE_L2_CACHE
114 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
115 #define CONFIG_BTB /* toggle branch predition */
116 #define CONFIG_DDR_ECC
117 #ifdef CONFIG_DDR_ECC
118 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
119 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
122 #define CONFIG_ENABLE_36BIT_PHYS
124 #ifdef CONFIG_PHYS_64BIT
125 #define CONFIG_ADDR_MAP
126 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
129 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
130 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
131 #define CONFIG_SYS_MEMTEST_END 0x00400000
132 #define CONFIG_SYS_ALT_MEMTEST
133 #define CONFIG_PANIC_HANG /* do not reset board on panic */
136 * Config the L3 Cache as L3 SRAM
138 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
139 #ifdef CONFIG_PHYS_64BIT
140 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
142 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
144 #define CONFIG_SYS_L3_SIZE (1024 << 10)
145 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
147 #ifdef CONFIG_PHYS_64BIT
148 #define CONFIG_SYS_DCSRBAR 0xf0000000
149 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
153 #define CONFIG_ID_EEPROM
154 #define CONFIG_SYS_I2C_EEPROM_NXID
155 #define CONFIG_SYS_EEPROM_BUS_NUM 0
156 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
157 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
162 #define CONFIG_VERY_BIG_RAM
163 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
164 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
166 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
167 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
169 #define CONFIG_DDR_SPD
170 #define CONFIG_FSL_DDR3
172 #define CONFIG_SYS_SPD_BUS_NUM 1
173 #define SPD_EEPROM_ADDRESS1 0x51
174 #define SPD_EEPROM_ADDRESS2 0x52
175 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
176 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
179 * Local Bus Definitions
182 /* Set the local bus clock 1/8 of platform clock */
183 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
185 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
186 #ifdef CONFIG_PHYS_64BIT
187 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
189 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
192 #define CONFIG_SYS_FLASH_BR_PRELIM \
193 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
195 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
196 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
198 #define CONFIG_SYS_BR1_PRELIM \
199 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
200 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
202 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
203 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
204 #ifdef CONFIG_PHYS_64BIT
205 #define PIXIS_BASE_PHYS 0xfffdf0000ull
207 #define PIXIS_BASE_PHYS PIXIS_BASE
210 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
211 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
213 #define PIXIS_LBMAP_SWITCH 7
214 #define PIXIS_LBMAP_MASK 0xf0
215 #define PIXIS_LBMAP_SHIFT 4
216 #define PIXIS_LBMAP_ALTBANK 0x40
218 #define CONFIG_SYS_FLASH_QUIET_TEST
219 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
221 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
222 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
223 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
224 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
226 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
228 #if defined(CONFIG_RAMBOOT_PBL)
229 #define CONFIG_SYS_RAMBOOT
233 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
234 #define CONFIG_NAND_FSL_ELBC
235 #ifdef CONFIG_NAND_FSL_ELBC
236 #define CONFIG_SYS_NAND_BASE 0xffa00000
237 #ifdef CONFIG_PHYS_64BIT
238 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
240 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
243 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
244 #define CONFIG_SYS_MAX_NAND_DEVICE 1
245 #define CONFIG_MTD_NAND_VERIFY_WRITE
246 #define CONFIG_CMD_NAND
247 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
249 /* NAND flash config */
250 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
251 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
252 | BR_PS_8 /* Port Size = 8 bit */ \
253 | BR_MS_FCM /* MSEL = FCM */ \
255 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
256 | OR_FCM_PGS /* Large Page*/ \
265 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
266 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
267 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
268 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
270 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
271 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
272 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
273 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
275 #endif /* CONFIG_NAND_FSL_ELBC */
277 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
278 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
281 #define CONFIG_SYS_FLASH_EMPTY_INFO
282 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
283 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
285 #define CONFIG_BOARD_EARLY_INIT_F
286 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
287 #define CONFIG_MISC_INIT_R
289 #define CONFIG_HWCONFIG
291 /* define to use L1 as initial stack */
292 #define CONFIG_L1_INIT_RAM
293 #define CONFIG_SYS_INIT_RAM_LOCK
294 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
295 #ifdef CONFIG_PHYS_64BIT
296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
298 /* The assembler doesn't like typecast */
299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
300 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
301 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
307 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
309 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
310 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
312 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
313 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
315 /* Serial Port - controlled on board with jumper J8
319 #define CONFIG_CONS_INDEX 1
320 #define CONFIG_SYS_NS16550
321 #define CONFIG_SYS_NS16550_SERIAL
322 #define CONFIG_SYS_NS16550_REG_SIZE 1
323 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
325 #define CONFIG_SYS_BAUDRATE_TABLE \
326 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
328 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
329 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
330 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
331 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
333 /* Use the HUSH parser */
334 #define CONFIG_SYS_HUSH_PARSER
335 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
337 /* pass open firmware flat tree */
338 #define CONFIG_OF_LIBFDT
339 #define CONFIG_OF_BOARD_SETUP
340 #define CONFIG_OF_STDOUT_VIA_ALIAS
342 /* new uImage format support */
344 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
347 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
348 #define CONFIG_HARD_I2C /* I2C with hardware support */
349 #define CONFIG_I2C_MULTI_BUS
350 #define CONFIG_I2C_CMD_TREE
351 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
352 #define CONFIG_SYS_I2C_SLAVE 0x7F
353 #define CONFIG_SYS_I2C_OFFSET 0x118000
354 #define CONFIG_SYS_I2C2_OFFSET 0x118100
359 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
360 #ifdef CONFIG_PHYS_64BIT
361 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
363 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
365 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
367 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
368 #ifdef CONFIG_PHYS_64BIT
369 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
371 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
373 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
376 * eSPI - Enhanced SPI
378 #define CONFIG_FSL_ESPI
379 #define CONFIG_SPI_FLASH
380 #define CONFIG_SPI_FLASH_SPANSION
381 #define CONFIG_CMD_SF
382 #define CONFIG_SF_DEFAULT_SPEED 10000000
383 #define CONFIG_SF_DEFAULT_MODE 0
387 * Memory space is mapped 1-1, but I/O space must start from 0.
390 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
391 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
392 #ifdef CONFIG_PHYS_64BIT
393 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
394 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
396 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
397 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
399 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
400 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
401 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
402 #ifdef CONFIG_PHYS_64BIT
403 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
405 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
407 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
409 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
410 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
411 #ifdef CONFIG_PHYS_64BIT
412 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
413 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
415 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
416 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
418 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
419 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
420 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
421 #ifdef CONFIG_PHYS_64BIT
422 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
424 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
426 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
428 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
429 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
430 #ifdef CONFIG_PHYS_64BIT
431 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
432 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
434 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
435 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
437 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
438 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
439 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
440 #ifdef CONFIG_PHYS_64BIT
441 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
443 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
445 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
447 /* controller 4, Base address 203000 */
448 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
449 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
450 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
451 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
452 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
453 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
456 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
457 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
458 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
459 #ifdef CONFIG_PHYS_64BIT
460 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
462 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
464 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
465 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
466 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
467 #ifdef CONFIG_PHYS_64BIT
468 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
470 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
472 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
474 #define CONFIG_SYS_DPAA_FMAN
475 #define CONFIG_SYS_DPAA_PME
476 /* Default address of microcode for the Linux Fman driver */
477 #define CONFIG_SYS_FMAN_FW
478 #if defined(CONFIG_SPIFLASH)
480 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
481 * env, so we got 0x110000.
483 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000
484 #elif defined(CONFIG_SDCARD)
486 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
487 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
488 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
490 #define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130)
491 #elif defined(CONFIG_NAND)
492 #define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
494 #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
496 #define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
497 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
499 #ifdef CONFIG_SYS_DPAA_FMAN
500 #define CONFIG_FMAN_ENET
504 #define CONFIG_NET_MULTI
505 #define CONFIG_PCI_PNP /* do pci plug-and-play */
508 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
509 #define CONFIG_DOS_PARTITION
510 #endif /* CONFIG_PCI */
513 #ifdef CONFIG_FSL_SATA_V2
514 #define CONFIG_LIBATA
515 #define CONFIG_FSL_SATA
517 #define CONFIG_SYS_SATA_MAX_DEVICE 2
519 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
520 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
522 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
523 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
526 #define CONFIG_CMD_SATA
527 #define CONFIG_DOS_PARTITION
528 #define CONFIG_CMD_EXT2
531 #ifdef CONFIG_FMAN_ENET
532 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
533 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
534 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
535 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
536 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
538 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
539 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
540 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
541 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
542 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
544 #define CONFIG_SYS_TBIPA_VALUE 8
545 #define CONFIG_MII /* MII PHY management */
546 #define CONFIG_ETHPRIME "FM1@DTSEC1"
547 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
553 #define CONFIG_LOADS_ECHO /* echo on for serial download */
554 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
557 * Command line configuration.
559 #include <config_cmd_default.h>
561 #define CONFIG_CMD_DHCP
562 #define CONFIG_CMD_ELF
563 #define CONFIG_CMD_ERRATA
564 #define CONFIG_CMD_GREPENV
565 #define CONFIG_CMD_IRQ
566 #define CONFIG_CMD_I2C
567 #define CONFIG_CMD_MII
568 #define CONFIG_CMD_PING
569 #define CONFIG_CMD_SETEXPR
572 #define CONFIG_CMD_PCI
573 #define CONFIG_CMD_NET
579 #define CONFIG_CMD_USB
580 #define CONFIG_USB_STORAGE
581 #define CONFIG_USB_EHCI
582 #define CONFIG_USB_EHCI_FSL
583 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
584 #define CONFIG_CMD_EXT2
585 #define CONFIG_HAS_FSL_DR_USB
590 #define CONFIG_FSL_ESDHC
591 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
592 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
593 #define CONFIG_CMD_MMC
594 #define CONFIG_GENERIC_MMC
595 #define CONFIG_CMD_EXT2
596 #define CONFIG_CMD_FAT
597 #define CONFIG_DOS_PARTITION
601 * Miscellaneous configurable options
603 #define CONFIG_SYS_LONGHELP /* undef to save memory */
604 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
605 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
606 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
607 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
608 #ifdef CONFIG_CMD_KGDB
609 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
611 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
613 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
614 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
615 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
616 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
619 * For booting Linux, the board info and command line data
620 * have to be in the first 64 MB of memory, since this is
621 * the maximum mapped by the Linux kernel during initialization.
623 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
624 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
626 #ifdef CONFIG_CMD_KGDB
627 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
628 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
632 * Environment Configuration
634 #define CONFIG_ROOTPATH /opt/nfsroot
635 #define CONFIG_BOOTFILE uImage
636 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
638 /* default location for tftp and bootm */
639 #define CONFIG_LOADADDR 1000000
641 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
643 #define CONFIG_BAUDRATE 115200
645 #if defined(CONFIG_P4080DS)
646 #define __USB_PHY_TYPE ulpi
648 #define __USB_PHY_TYPE utmi
651 #define CONFIG_EXTRA_ENV_SETTINGS \
652 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
653 "bank_intlv=cs0_cs1;" \
654 "usb1:dr_mode=host,phy_type=" MK_STR(__USB_PHY_TYPE) "\0"\
656 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
657 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
658 "tftpflash=tftpboot $loadaddr $uboot && " \
659 "protect off $ubootaddr +$filesize && " \
660 "erase $ubootaddr +$filesize && " \
661 "cp.b $loadaddr $ubootaddr $filesize && " \
662 "protect on $ubootaddr +$filesize && " \
663 "cmp.b $loadaddr $ubootaddr $filesize\0" \
664 "consoledev=ttyS0\0" \
665 "ramdiskaddr=2000000\0" \
666 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
668 "fdtfile=p4080ds/p4080ds.dtb\0" \
672 #define CONFIG_HDBOOT \
673 "setenv bootargs root=/dev/$bdev rw " \
674 "console=$consoledev,$baudrate $othbootargs;" \
675 "tftp $loadaddr $bootfile;" \
676 "tftp $fdtaddr $fdtfile;" \
677 "bootm $loadaddr - $fdtaddr"
679 #define CONFIG_NFSBOOTCOMMAND \
680 "setenv bootargs root=/dev/nfs rw " \
681 "nfsroot=$serverip:$rootpath " \
682 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
683 "console=$consoledev,$baudrate $othbootargs;" \
684 "tftp $loadaddr $bootfile;" \
685 "tftp $fdtaddr $fdtfile;" \
686 "bootm $loadaddr - $fdtaddr"
688 #define CONFIG_RAMBOOTCOMMAND \
689 "setenv bootargs root=/dev/ram rw " \
690 "console=$consoledev,$baudrate $othbootargs;" \
691 "tftp $ramdiskaddr $ramdiskfile;" \
692 "tftp $loadaddr $bootfile;" \
693 "tftp $fdtaddr $fdtfile;" \
694 "bootm $loadaddr $ramdiskaddr $fdtaddr"
696 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
698 #endif /* __CONFIG_H */