include/configs/corenet_ds.h

   1 /*
   2  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Corenet DS style board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include "../board/freescale/common/ics307_clk.h"
  14
  15 #ifdef CONFIG_RAMBOOT_PBL
  16 #ifdef CONFIG_SECURE_BOOT
  17 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  19 #ifdef CONFIG_NAND
  20 #define CONFIG_RAMBOOT_NAND
  21 #endif
  22 #define CONFIG_BOOTSCRIPT_COPY_RAM
  23 #else
  24 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  25 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  27 #if defined(CONFIG_TARGET_P3041DS)
  28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
  29 #elif defined(CONFIG_TARGET_P4080DS)
  30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
  31 #elif defined(CONFIG_TARGET_P5020DS)
  32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
  33 #elif defined(CONFIG_TARGET_P5040DS)
  34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
  35 #endif
  36 #endif
  37 #endif
  38
  39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  40 /* Set 1M boot space */
  41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  43                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  45 #define CONFIG_SYS_NO_FLASH
  46 #endif
  47
  48 /* High Level Configuration Options */
  49 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  50 #define CONFIG_MP                       /* support multiple processors */
  51
  52 #ifndef CONFIG_SYS_TEXT_BASE
  53 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  54 #endif
  55
  56 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  57 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  58 #endif
  59
  60 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  61 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  62 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  63 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  64 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  65 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  66 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  67 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  68
  69 #define CONFIG_ENV_OVERWRITE
  70
  71 #ifdef CONFIG_SYS_NO_FLASH
  72 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
  73 #define CONFIG_ENV_IS_NOWHERE
  74 #endif
  75 #else
  76 #define CONFIG_FLASH_CFI_DRIVER
  77 #define CONFIG_SYS_FLASH_CFI
  78 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  79 #endif
  80
  81 #if defined(CONFIG_SPIFLASH)
  82 #define CONFIG_SYS_EXTRA_ENV_RELOC
  83 #define CONFIG_ENV_IS_IN_SPI_FLASH
  84 #define CONFIG_ENV_SPI_BUS              0
  85 #define CONFIG_ENV_SPI_CS               0
  86 #define CONFIG_ENV_SPI_MAX_HZ           10000000
  87 #define CONFIG_ENV_SPI_MODE             0
  88 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  89 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  90 #define CONFIG_ENV_SECT_SIZE            0x10000
  91 #elif defined(CONFIG_SDCARD)
  92 #define CONFIG_SYS_EXTRA_ENV_RELOC
  93 #define CONFIG_ENV_IS_IN_MMC
  94 #define CONFIG_FSL_FIXED_MMC_LOCATION
  95 #define CONFIG_SYS_MMC_ENV_DEV          0
  96 #define CONFIG_ENV_SIZE                 0x2000
  97 #define CONFIG_ENV_OFFSET               (512 * 1658)
  98 #elif defined(CONFIG_NAND)
  99 #define CONFIG_SYS_EXTRA_ENV_RELOC
 100 #define CONFIG_ENV_IS_IN_NAND
 101 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 102 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 103 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 104 #define CONFIG_ENV_IS_IN_REMOTE
 105 #define CONFIG_ENV_ADDR         0xffe20000
 106 #define CONFIG_ENV_SIZE         0x2000
 107 #elif defined(CONFIG_ENV_IS_NOWHERE)
 108 #define CONFIG_ENV_SIZE         0x2000
 109 #else
 110 #define CONFIG_ENV_IS_IN_FLASH
 111 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 112 #define CONFIG_ENV_SIZE         0x2000
 113 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 114 #endif
 115
 116 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 117
 118 /*
 119  * These can be toggled for performance analysis, otherwise use default.
 120  */
 121 #define CONFIG_SYS_CACHE_STASHING
 122 #define CONFIG_BACKSIDE_L2_CACHE
 123 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 124 #define CONFIG_BTB                      /* toggle branch predition */
 125 #define CONFIG_DDR_ECC
 126 #ifdef CONFIG_DDR_ECC
 127 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 128 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 129 #endif
 130
 131 #define CONFIG_ENABLE_36BIT_PHYS
 132
 133 #ifdef CONFIG_PHYS_64BIT
 134 #define CONFIG_ADDR_MAP
 135 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 136 #endif
 137
 138 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 139 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 140 #define CONFIG_SYS_MEMTEST_END          0x00400000
 141 #define CONFIG_SYS_ALT_MEMTEST
 142 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 143
 144 /*
 145  *  Config the L3 Cache as L3 SRAM
 146  */
 147 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 148 #ifdef CONFIG_PHYS_64BIT
 149 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
 150 #else
 151 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 152 #endif
 153 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 154 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 155
 156 #ifdef CONFIG_PHYS_64BIT
 157 #define CONFIG_SYS_DCSRBAR              0xf0000000
 158 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 159 #endif
 160
 161 /* EEPROM */
 162 #define CONFIG_ID_EEPROM
 163 #define CONFIG_SYS_I2C_EEPROM_NXID
 164 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 165 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 167
 168 /*
 169  * DDR Setup
 170  */
 171 #define CONFIG_VERY_BIG_RAM
 172 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 173 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 174
 175 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 176 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 177
 178 #define CONFIG_DDR_SPD
 179
 180 #define CONFIG_SYS_SPD_BUS_NUM  1
 181 #define SPD_EEPROM_ADDRESS1     0x51
 182 #define SPD_EEPROM_ADDRESS2     0x52
 183 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 184 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 185
 186 /*
 187  * Local Bus Definitions
 188  */
 189
 190 /* Set the local bus clock 1/8 of platform clock */
 191 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 192
 193 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
 194 #ifdef CONFIG_PHYS_64BIT
 195 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 196 #else
 197 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 198 #endif
 199
 200 #define CONFIG_SYS_FLASH_BR_PRELIM \
 201                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
 202                  | BR_PS_16 | BR_V)
 203 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 204                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 205
 206 #define CONFIG_SYS_BR1_PRELIM \
 207         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 208 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 209
 210 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 211 #ifdef CONFIG_PHYS_64BIT
 212 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 213 #else
 214 #define PIXIS_BASE_PHYS         PIXIS_BASE
 215 #endif
 216
 217 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 218 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 219
 220 #define PIXIS_LBMAP_SWITCH      7
 221 #define PIXIS_LBMAP_MASK        0xf0
 222 #define PIXIS_LBMAP_SHIFT       4
 223 #define PIXIS_LBMAP_ALTBANK     0x40
 224
 225 #define CONFIG_SYS_FLASH_QUIET_TEST
 226 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 227
 228 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 229 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 230 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 231 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 232
 233 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 234
 235 #if defined(CONFIG_RAMBOOT_PBL)
 236 #define CONFIG_SYS_RAMBOOT
 237 #endif
 238
 239 /* Nand Flash */
 240 #ifdef CONFIG_NAND_FSL_ELBC
 241 #define CONFIG_SYS_NAND_BASE            0xffa00000
 242 #ifdef CONFIG_PHYS_64BIT
 243 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 244 #else
 245 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 246 #endif
 247
 248 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 249 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 250 #define CONFIG_CMD_NAND
 251 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 252
 253 /* NAND flash config */
 254 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 255                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 256                                | BR_PS_8               /* Port Size = 8 bit */ \
 257                                | BR_MS_FCM             /* MSEL = FCM */ \
 258                                | BR_V)                 /* valid */
 259 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 260                                | OR_FCM_PGS            /* Large Page*/ \
 261                                | OR_FCM_CSCT \
 262                                | OR_FCM_CST \
 263                                | OR_FCM_CHT \
 264                                | OR_FCM_SCY_1 \
 265                                | OR_FCM_TRLX \
 266                                | OR_FCM_EHTR)
 267
 268 #ifdef CONFIG_NAND
 269 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 270 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 271 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 272 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 273 #else
 274 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 275 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 276 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 277 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 278 #endif
 279 #else
 280 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 281 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 282 #endif /* CONFIG_NAND_FSL_ELBC */
 283
 284 #define CONFIG_SYS_FLASH_EMPTY_INFO
 285 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 286 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 287
 288 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 289 #define CONFIG_MISC_INIT_R
 290
 291 #define CONFIG_HWCONFIG
 292
 293 /* define to use L1 as initial stack */
 294 #define CONFIG_L1_INIT_RAM
 295 #define CONFIG_SYS_INIT_RAM_LOCK
 296 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 297 #ifdef CONFIG_PHYS_64BIT
 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 300 /* The assembler doesn't like typecast */
 301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 302         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 303           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 304 #else
 305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 308 #endif
 309 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 310
 311 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 312 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 313
 314 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 315 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 316
 317 /* Serial Port - controlled on board with jumper J8
 318  * open - index 2
 319  * shorted - index 1
 320  */
 321 #define CONFIG_CONS_INDEX       1
 322 #define CONFIG_SYS_NS16550_SERIAL
 323 #define CONFIG_SYS_NS16550_REG_SIZE     1
 324 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 325
 326 #define CONFIG_SYS_BAUDRATE_TABLE       \
 327         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 328
 329 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 330 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 331 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 332 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 333
 334 /* I2C */
 335 #define CONFIG_SYS_I2C
 336 #define CONFIG_SYS_I2C_FSL
 337 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 338 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 339 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 340 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 341 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 342 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 343
 344 /*
 345  * RapidIO
 346  */
 347 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 348 #ifdef CONFIG_PHYS_64BIT
 349 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 350 #else
 351 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 352 #endif
 353 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 354
 355 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 356 #ifdef CONFIG_PHYS_64BIT
 357 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 358 #else
 359 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 360 #endif
 361 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 362
 363 /*
 364  * for slave u-boot IMAGE instored in master memory space,
 365  * PHYS must be aligned based on the SIZE
 366  */
 367 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 368 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 369 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 370 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 371 /*
 372  * for slave UCODE and ENV instored in master memory space,
 373  * PHYS must be aligned based on the SIZE
 374  */
 375 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 376 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 377 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 378
 379 /* slave core release by master*/
 380 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 381 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 382
 383 /*
 384  * SRIO_PCIE_BOOT - SLAVE
 385  */
 386 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 387 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 388 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 389                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 390 #endif
 391
 392 /*
 393  * eSPI - Enhanced SPI
 394  */
 395 #define CONFIG_SF_DEFAULT_SPEED         10000000
 396 #define CONFIG_SF_DEFAULT_MODE          0
 397
 398 /*
 399  * General PCI
 400  * Memory space is mapped 1-1, but I/O space must start from 0.
 401  */
 402
 403 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 404 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 405 #ifdef CONFIG_PHYS_64BIT
 406 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 407 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 408 #else
 409 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 410 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 411 #endif
 412 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 413 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 414 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 415 #ifdef CONFIG_PHYS_64BIT
 416 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 417 #else
 418 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 419 #endif
 420 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 421
 422 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 423 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 424 #ifdef CONFIG_PHYS_64BIT
 425 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 426 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 427 #else
 428 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 429 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 430 #endif
 431 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 432 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 433 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 434 #ifdef CONFIG_PHYS_64BIT
 435 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 436 #else
 437 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 438 #endif
 439 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 440
 441 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 442 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 443 #ifdef CONFIG_PHYS_64BIT
 444 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 445 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 446 #else
 447 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 448 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 449 #endif
 450 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 451 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 452 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 453 #ifdef CONFIG_PHYS_64BIT
 454 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 455 #else
 456 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 457 #endif
 458 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 459
 460 /* controller 4, Base address 203000 */
 461 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 462 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 463 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 464 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 465 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 466 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 467
 468 /* Qman/Bman */
 469 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 470 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 471 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 472 #ifdef CONFIG_PHYS_64BIT
 473 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 474 #else
 475 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 476 #endif
 477 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 478 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 479 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 480 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 481 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 482 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 483                                         CONFIG_SYS_BMAN_CENA_SIZE)
 484 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 485 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 486 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 487 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 488 #ifdef CONFIG_PHYS_64BIT
 489 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 490 #else
 491 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 492 #endif
 493 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 494 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 495 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 496 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 497 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 498 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 499                                         CONFIG_SYS_QMAN_CENA_SIZE)
 500 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 501 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 502
 503 #define CONFIG_SYS_DPAA_FMAN
 504 #define CONFIG_SYS_DPAA_PME
 505 /* Default address of microcode for the Linux Fman driver */
 506 #if defined(CONFIG_SPIFLASH)
 507 /*
 508  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 509  * env, so we got 0x110000.
 510  */
 511 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 512 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 513 #elif defined(CONFIG_SDCARD)
 514 /*
 515  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 516  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 517  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 518  */
 519 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 520 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 521 #elif defined(CONFIG_NAND)
 522 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 523 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 524 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 525 /*
 526  * Slave has no ucode locally, it can fetch this from remote. When implementing
 527  * in two corenet boards, slave's ucode could be stored in master's memory
 528  * space, the address can be mapped from slave TLB->slave LAW->
 529  * slave SRIO or PCIE outbound window->master inbound window->
 530  * master LAW->the ucode address in master's memory space.
 531  */
 532 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 533 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 534 #else
 535 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 536 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 537 #endif
 538 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 539 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 540
 541 #ifdef CONFIG_SYS_DPAA_FMAN
 542 #define CONFIG_FMAN_ENET
 543 #define CONFIG_PHYLIB_10G
 544 #define CONFIG_PHY_VITESSE
 545 #define CONFIG_PHY_TERANETICS
 546 #endif
 547
 548 #ifdef CONFIG_PCI
 549 #define CONFIG_PCI_INDIRECT_BRIDGE
 550
 551 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 552 #endif  /* CONFIG_PCI */
 553
 554 /* SATA */
 555 #ifdef CONFIG_FSL_SATA_V2
 556 #define CONFIG_LIBATA
 557 #define CONFIG_FSL_SATA
 558
 559 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 560 #define CONFIG_SATA1
 561 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 562 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 563 #define CONFIG_SATA2
 564 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 565 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 566
 567 #define CONFIG_LBA48
 568 #define CONFIG_CMD_SATA
 569 #endif
 570
 571 #ifdef CONFIG_FMAN_ENET
 572 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 573 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 574 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 575 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 576 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 577
 578 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 579 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 580 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 581 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 582 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 583
 584 #define CONFIG_SYS_TBIPA_VALUE  8
 585 #define CONFIG_MII              /* MII PHY management */
 586 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 587 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 588 #endif
 589
 590 /*
 591  * Environment
 592  */
 593 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 594 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 595
 596 /*
 597  * Command line configuration.
 598  */
 599 #define CONFIG_CMD_ERRATA
 600 #define CONFIG_CMD_IRQ
 601 #define CONFIG_CMD_REGINFO
 602
 603 #ifdef CONFIG_PCI
 604 #define CONFIG_CMD_PCI
 605 #endif
 606
 607 /*
 608 * USB
 609 */
 610 #define CONFIG_HAS_FSL_DR_USB
 611 #define CONFIG_HAS_FSL_MPH_USB
 612
 613 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 614 #define CONFIG_USB_EHCI
 615 #define CONFIG_USB_EHCI_FSL
 616 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 617 #endif
 618
 619 #ifdef CONFIG_MMC
 620 #define CONFIG_FSL_ESDHC
 621 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 622 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 623 #define CONFIG_GENERIC_MMC
 624 #endif
 625
 626 /* Hash command with SHA acceleration supported in hardware */
 627 #ifdef CONFIG_FSL_CAAM
 628 #define CONFIG_CMD_HASH
 629 #define CONFIG_SHA_HW_ACCEL
 630 #endif
 631
 632 /*
 633  * Miscellaneous configurable options
 634  */
 635 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 636 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 637 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 638 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 639 #ifdef CONFIG_CMD_KGDB
 640 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 641 #else
 642 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 643 #endif
 644 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 645 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 646 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 647
 648 /*
 649  * For booting Linux, the board info and command line data
 650  * have to be in the first 64 MB of memory, since this is
 651  * the maximum mapped by the Linux kernel during initialization.
 652  */
 653 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 654 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 655
 656 #ifdef CONFIG_CMD_KGDB
 657 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 658 #endif
 659
 660 /*
 661  * Environment Configuration
 662  */
 663 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 664 #define CONFIG_BOOTFILE         "uImage"
 665 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 666
 667 /* default location for tftp and bootm */
 668 #define CONFIG_LOADADDR         1000000
 669
 670
 671 #define CONFIG_BAUDRATE 115200
 672
 673 #ifdef CONFIG_TARGET_P4080DS
 674 #define __USB_PHY_TYPE  ulpi
 675 #else
 676 #define __USB_PHY_TYPE  utmi
 677 #endif
 678
 679 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 680         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 681         "bank_intlv=cs0_cs1;"                                   \
 682         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 683         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 684         "netdev=eth0\0"                                         \
 685         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 686         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 687         "tftpflash=tftpboot $loadaddr $uboot && "               \
 688         "protect off $ubootaddr +$filesize && "                 \
 689         "erase $ubootaddr +$filesize && "                       \
 690         "cp.b $loadaddr $ubootaddr $filesize && "               \
 691         "protect on $ubootaddr +$filesize && "                  \
 692         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 693         "consoledev=ttyS0\0"                                    \
 694         "ramdiskaddr=2000000\0"                                 \
 695         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 696         "fdtaddr=1e00000\0"                                     \
 697         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 698         "bdev=sda3\0"
 699
 700 #define CONFIG_HDBOOT                                   \
 701         "setenv bootargs root=/dev/$bdev rw "           \
 702         "console=$consoledev,$baudrate $othbootargs;"   \
 703         "tftp $loadaddr $bootfile;"                     \
 704         "tftp $fdtaddr $fdtfile;"                       \
 705         "bootm $loadaddr - $fdtaddr"
 706
 707 #define CONFIG_NFSBOOTCOMMAND                   \
 708         "setenv bootargs root=/dev/nfs rw "     \
 709         "nfsroot=$serverip:$rootpath "          \
 710         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 711         "console=$consoledev,$baudrate $othbootargs;"   \
 712         "tftp $loadaddr $bootfile;"             \
 713         "tftp $fdtaddr $fdtfile;"               \
 714         "bootm $loadaddr - $fdtaddr"
 715
 716 #define CONFIG_RAMBOOTCOMMAND                           \
 717         "setenv bootargs root=/dev/ram rw "             \
 718         "console=$consoledev,$baudrate $othbootargs;"   \
 719         "tftp $ramdiskaddr $ramdiskfile;"               \
 720         "tftp $loadaddr $bootfile;"                     \
 721         "tftp $fdtaddr $fdtfile;"                       \
 722         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 723
 724 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 725
 726 #include <asm/fsl_secure_boot.h>
 727
 728 #endif  /* __CONFIG_H */