include/configs/corenet_ds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * Corenet DS style board configuration file
   8  */
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include "../board/freescale/common/ics307_clk.h"
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #ifdef CONFIG_SECURE_BOOT
  16 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  17 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  18 #ifdef CONFIG_NAND
  19 #define CONFIG_RAMBOOT_NAND
  20 #endif
  21 #define CONFIG_BOOTSCRIPT_COPY_RAM
  22 #else
  23 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  24 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  25 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  26 #if defined(CONFIG_TARGET_P3041DS)
  27 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
  28 #elif defined(CONFIG_TARGET_P4080DS)
  29 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
  30 #elif defined(CONFIG_TARGET_P5020DS)
  31 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
  32 #elif defined(CONFIG_TARGET_P5040DS)
  33 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
  34 #endif
  35 #endif
  36 #endif
  37
  38 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  39 /* Set 1M boot space */
  40 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  42                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  43 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  44 #endif
  45
  46 /* High Level Configuration Options */
  47 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  48
  49 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  50 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  51 #endif
  52
  53 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  54 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  55 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  56 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  57 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  58
  59 #define CONFIG_ENV_OVERWRITE
  60
  61 #if defined(CONFIG_SPIFLASH)
  62 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  63 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  64 #define CONFIG_ENV_SECT_SIZE            0x10000
  65 #elif defined(CONFIG_SDCARD)
  66 #define CONFIG_FSL_FIXED_MMC_LOCATION
  67 #define CONFIG_SYS_MMC_ENV_DEV          0
  68 #define CONFIG_ENV_SIZE                 0x2000
  69 #define CONFIG_ENV_OFFSET               (512 * 1658)
  70 #elif defined(CONFIG_NAND)
  71 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
  72 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  73 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  74 #define CONFIG_ENV_ADDR         0xffe20000
  75 #define CONFIG_ENV_SIZE         0x2000
  76 #elif defined(CONFIG_ENV_IS_NOWHERE)
  77 #define CONFIG_ENV_SIZE         0x2000
  78 #else
  79 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  80 #define CONFIG_ENV_SIZE         0x2000
  81 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
  82 #endif
  83
  84 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  85
  86 /*
  87  * These can be toggled for performance analysis, otherwise use default.
  88  */
  89 #define CONFIG_SYS_CACHE_STASHING
  90 #define CONFIG_BACKSIDE_L2_CACHE
  91 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  92 #define CONFIG_BTB                      /* toggle branch predition */
  93 #define CONFIG_DDR_ECC
  94 #ifdef CONFIG_DDR_ECC
  95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  96 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  97 #endif
  98
  99 #define CONFIG_ENABLE_36BIT_PHYS
 100
 101 #ifdef CONFIG_PHYS_64BIT
 102 #define CONFIG_ADDR_MAP
 103 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 104 #endif
 105
 106 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 107 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 108 #define CONFIG_SYS_MEMTEST_END          0x00400000
 109
 110 /*
 111  *  Config the L3 Cache as L3 SRAM
 112  */
 113 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 114 #ifdef CONFIG_PHYS_64BIT
 115 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
 116 #else
 117 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 118 #endif
 119 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 120 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 121
 122 #ifdef CONFIG_PHYS_64BIT
 123 #define CONFIG_SYS_DCSRBAR              0xf0000000
 124 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 125 #endif
 126
 127 /* EEPROM */
 128 #define CONFIG_ID_EEPROM
 129 #define CONFIG_SYS_I2C_EEPROM_NXID
 130 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 131 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 132 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 133
 134 /*
 135  * DDR Setup
 136  */
 137 #define CONFIG_VERY_BIG_RAM
 138 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 139 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 140
 141 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 142 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 143
 144 #define CONFIG_DDR_SPD
 145
 146 #define CONFIG_SYS_SPD_BUS_NUM  1
 147 #define SPD_EEPROM_ADDRESS1     0x51
 148 #define SPD_EEPROM_ADDRESS2     0x52
 149 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 150 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 151
 152 /*
 153  * Local Bus Definitions
 154  */
 155
 156 /* Set the local bus clock 1/8 of platform clock */
 157 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 158
 159 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
 160 #ifdef CONFIG_PHYS_64BIT
 161 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 162 #else
 163 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 164 #endif
 165
 166 #define CONFIG_SYS_FLASH_BR_PRELIM \
 167                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
 168                  | BR_PS_16 | BR_V)
 169 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 170                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 171
 172 #define CONFIG_SYS_BR1_PRELIM \
 173         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 174 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 175
 176 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 177 #ifdef CONFIG_PHYS_64BIT
 178 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 179 #else
 180 #define PIXIS_BASE_PHYS         PIXIS_BASE
 181 #endif
 182
 183 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 184 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 185
 186 #define PIXIS_LBMAP_SWITCH      7
 187 #define PIXIS_LBMAP_MASK        0xf0
 188 #define PIXIS_LBMAP_SHIFT       4
 189 #define PIXIS_LBMAP_ALTBANK     0x40
 190
 191 #define CONFIG_SYS_FLASH_QUIET_TEST
 192 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 193
 194 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 195 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 196 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 197 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 198
 199 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 200
 201 #if defined(CONFIG_RAMBOOT_PBL)
 202 #define CONFIG_SYS_RAMBOOT
 203 #endif
 204
 205 /* Nand Flash */
 206 #ifdef CONFIG_NAND_FSL_ELBC
 207 #define CONFIG_SYS_NAND_BASE            0xffa00000
 208 #ifdef CONFIG_PHYS_64BIT
 209 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 210 #else
 211 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 212 #endif
 213
 214 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 215 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 216 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 217
 218 /* NAND flash config */
 219 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 220                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 221                                | BR_PS_8               /* Port Size = 8 bit */ \
 222                                | BR_MS_FCM             /* MSEL = FCM */ \
 223                                | BR_V)                 /* valid */
 224 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 225                                | OR_FCM_PGS            /* Large Page*/ \
 226                                | OR_FCM_CSCT \
 227                                | OR_FCM_CST \
 228                                | OR_FCM_CHT \
 229                                | OR_FCM_SCY_1 \
 230                                | OR_FCM_TRLX \
 231                                | OR_FCM_EHTR)
 232
 233 #ifdef CONFIG_NAND
 234 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 235 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 236 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 237 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 238 #else
 239 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 240 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 241 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 242 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 243 #endif
 244 #else
 245 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 246 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 247 #endif /* CONFIG_NAND_FSL_ELBC */
 248
 249 #define CONFIG_SYS_FLASH_EMPTY_INFO
 250 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 251 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 252
 253 #define CONFIG_HWCONFIG
 254
 255 /* define to use L1 as initial stack */
 256 #define CONFIG_L1_INIT_RAM
 257 #define CONFIG_SYS_INIT_RAM_LOCK
 258 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 259 #ifdef CONFIG_PHYS_64BIT
 260 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 261 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 262 /* The assembler doesn't like typecast */
 263 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 264         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 265           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 266 #else
 267 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 268 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 269 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 270 #endif
 271 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 272
 273 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 274 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 275
 276 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 277 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 278
 279 /* Serial Port - controlled on board with jumper J8
 280  * open - index 2
 281  * shorted - index 1
 282  */
 283 #define CONFIG_SYS_NS16550_SERIAL
 284 #define CONFIG_SYS_NS16550_REG_SIZE     1
 285 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 286
 287 #define CONFIG_SYS_BAUDRATE_TABLE       \
 288         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 289
 290 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 291 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 292 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 293 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 294
 295 /* I2C */
 296 #define CONFIG_SYS_I2C
 297 #define CONFIG_SYS_I2C_FSL
 298 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 299 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 300 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 301 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 302 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 303 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 304
 305 /*
 306  * RapidIO
 307  */
 308 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 309 #ifdef CONFIG_PHYS_64BIT
 310 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 311 #else
 312 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 313 #endif
 314 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 315
 316 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 317 #ifdef CONFIG_PHYS_64BIT
 318 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 319 #else
 320 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 321 #endif
 322 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 323
 324 /*
 325  * for slave u-boot IMAGE instored in master memory space,
 326  * PHYS must be aligned based on the SIZE
 327  */
 328 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 329 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 330 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 331 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 332 /*
 333  * for slave UCODE and ENV instored in master memory space,
 334  * PHYS must be aligned based on the SIZE
 335  */
 336 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 337 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 338 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 339
 340 /* slave core release by master*/
 341 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 342 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 343
 344 /*
 345  * SRIO_PCIE_BOOT - SLAVE
 346  */
 347 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 348 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 349 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 350                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 351 #endif
 352
 353 /*
 354  * eSPI - Enhanced SPI
 355  */
 356
 357 /*
 358  * General PCI
 359  * Memory space is mapped 1-1, but I/O space must start from 0.
 360  */
 361
 362 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 363 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 364 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 365 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 366 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 367
 368 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 369 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 370 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 371 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 372 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 373
 374 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 375 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 376 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 377 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 378 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 379
 380 /* controller 4, Base address 203000 */
 381 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 382 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 383
 384 /* Qman/Bman */
 385 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 386 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 387 #ifdef CONFIG_PHYS_64BIT
 388 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 389 #else
 390 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 391 #endif
 392 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 393 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 394 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 395 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 396 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 397 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 398                                         CONFIG_SYS_BMAN_CENA_SIZE)
 399 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 400 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 401 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 402 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 403 #ifdef CONFIG_PHYS_64BIT
 404 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 405 #else
 406 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 407 #endif
 408 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 409 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 410 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 411 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 412 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 413 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 414                                         CONFIG_SYS_QMAN_CENA_SIZE)
 415 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 416 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 417
 418 #define CONFIG_SYS_DPAA_FMAN
 419 #define CONFIG_SYS_DPAA_PME
 420 /* Default address of microcode for the Linux Fman driver */
 421 #if defined(CONFIG_SPIFLASH)
 422 /*
 423  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 424  * env, so we got 0x110000.
 425  */
 426 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 427 #elif defined(CONFIG_SDCARD)
 428 /*
 429  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 430  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 431  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 432  */
 433 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 434 #elif defined(CONFIG_NAND)
 435 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 436 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 437 /*
 438  * Slave has no ucode locally, it can fetch this from remote. When implementing
 439  * in two corenet boards, slave's ucode could be stored in master's memory
 440  * space, the address can be mapped from slave TLB->slave LAW->
 441  * slave SRIO or PCIE outbound window->master inbound window->
 442  * master LAW->the ucode address in master's memory space.
 443  */
 444 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 445 #else
 446 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 447 #endif
 448 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 449 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 450
 451 #ifdef CONFIG_SYS_DPAA_FMAN
 452 #define CONFIG_PHYLIB_10G
 453 #define CONFIG_PHY_VITESSE
 454 #define CONFIG_PHY_TERANETICS
 455 #endif
 456
 457 #ifdef CONFIG_PCI
 458 #if !defined(CONFIG_DM_PCI)
 459 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 460 #define CONFIG_PCI_INDIRECT_BRIDGE
 461 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 462 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 463 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 464 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 465 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 466 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 467 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 468 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 469 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 470 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 471 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 472 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 473 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 474 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 475 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 476 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 477 #endif
 478
 479 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 480 #endif  /* CONFIG_PCI */
 481
 482 /* SATA */
 483 #ifdef CONFIG_FSL_SATA_V2
 484 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 485 #define CONFIG_SATA1
 486 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 487 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 488 #define CONFIG_SATA2
 489 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 490 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 491
 492 #define CONFIG_LBA48
 493 #endif
 494
 495 #ifdef CONFIG_FMAN_ENET
 496 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 497 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 498 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 499 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 500 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 501
 502 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 503 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 504 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 505 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 506 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 507
 508 #define CONFIG_SYS_TBIPA_VALUE  8
 509 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 510 #endif
 511
 512 /*
 513  * Environment
 514  */
 515 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 516 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 517
 518 /*
 519 * USB
 520 */
 521 #define CONFIG_HAS_FSL_DR_USB
 522 #define CONFIG_HAS_FSL_MPH_USB
 523
 524 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 525 #define CONFIG_USB_EHCI_FSL
 526 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 527 #endif
 528
 529 #ifdef CONFIG_MMC
 530 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 531 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 532 #endif
 533
 534 /*
 535  * Miscellaneous configurable options
 536  */
 537 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 538
 539 /*
 540  * For booting Linux, the board info and command line data
 541  * have to be in the first 64 MB of memory, since this is
 542  * the maximum mapped by the Linux kernel during initialization.
 543  */
 544 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 545 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 546
 547 #ifdef CONFIG_CMD_KGDB
 548 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 549 #endif
 550
 551 /*
 552  * Environment Configuration
 553  */
 554 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 555 #define CONFIG_BOOTFILE         "uImage"
 556 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 557
 558 /* default location for tftp and bootm */
 559 #define CONFIG_LOADADDR         1000000
 560
 561 #ifdef CONFIG_TARGET_P4080DS
 562 #define __USB_PHY_TYPE  ulpi
 563 #else
 564 #define __USB_PHY_TYPE  utmi
 565 #endif
 566
 567 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 568         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 569         "bank_intlv=cs0_cs1;"                                   \
 570         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 571         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 572         "netdev=eth0\0"                                         \
 573         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 574         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 575         "tftpflash=tftpboot $loadaddr $uboot && "               \
 576         "protect off $ubootaddr +$filesize && "                 \
 577         "erase $ubootaddr +$filesize && "                       \
 578         "cp.b $loadaddr $ubootaddr $filesize && "               \
 579         "protect on $ubootaddr +$filesize && "                  \
 580         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 581         "consoledev=ttyS0\0"                                    \
 582         "ramdiskaddr=2000000\0"                                 \
 583         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 584         "fdtaddr=1e00000\0"                                     \
 585         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 586         "bdev=sda3\0"
 587
 588 #define CONFIG_HDBOOT                                   \
 589         "setenv bootargs root=/dev/$bdev rw "           \
 590         "console=$consoledev,$baudrate $othbootargs;"   \
 591         "tftp $loadaddr $bootfile;"                     \
 592         "tftp $fdtaddr $fdtfile;"                       \
 593         "bootm $loadaddr - $fdtaddr"
 594
 595 #define CONFIG_NFSBOOTCOMMAND                   \
 596         "setenv bootargs root=/dev/nfs rw "     \
 597         "nfsroot=$serverip:$rootpath "          \
 598         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 599         "console=$consoledev,$baudrate $othbootargs;"   \
 600         "tftp $loadaddr $bootfile;"             \
 601         "tftp $fdtaddr $fdtfile;"               \
 602         "bootm $loadaddr - $fdtaddr"
 603
 604 #define CONFIG_RAMBOOTCOMMAND                           \
 605         "setenv bootargs root=/dev/ram rw "             \
 606         "console=$consoledev,$baudrate $othbootargs;"   \
 607         "tftp $ramdiskaddr $ramdiskfile;"               \
 608         "tftp $loadaddr $bootfile;"                     \
 609         "tftp $fdtaddr $fdtfile;"                       \
 610         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 611
 612 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 613
 614 #include <asm/fsl_secure_boot.h>
 615
 616 #endif  /* __CONFIG_H */