include/configs/corenet_ds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * Corenet DS style board configuration file
   8  */
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include "../board/freescale/common/ics307_clk.h"
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #ifdef CONFIG_SECURE_BOOT
  16 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  17 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  18 #ifdef CONFIG_NAND
  19 #define CONFIG_RAMBOOT_NAND
  20 #endif
  21 #define CONFIG_BOOTSCRIPT_COPY_RAM
  22 #else
  23 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  24 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  25 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  26 #if defined(CONFIG_TARGET_P3041DS)
  27 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
  28 #elif defined(CONFIG_TARGET_P4080DS)
  29 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
  30 #elif defined(CONFIG_TARGET_P5020DS)
  31 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
  32 #elif defined(CONFIG_TARGET_P5040DS)
  33 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
  34 #endif
  35 #endif
  36 #endif
  37
  38 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  39 /* Set 1M boot space */
  40 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  42                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  43 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  44 #endif
  45
  46 /* High Level Configuration Options */
  47 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  48
  49 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  50 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  51 #endif
  52
  53 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  54 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  55 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  56 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  57 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  58 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  59
  60 #define CONFIG_ENV_OVERWRITE
  61
  62 #ifndef CONFIG_MTD_NOR_FLASH
  63 #else
  64 #define CONFIG_FLASH_CFI_DRIVER
  65 #define CONFIG_SYS_FLASH_CFI
  66 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  67 #endif
  68
  69 #if defined(CONFIG_SPIFLASH)
  70 #define CONFIG_SYS_EXTRA_ENV_RELOC
  71 #define CONFIG_ENV_SPI_BUS              0
  72 #define CONFIG_ENV_SPI_CS               0
  73 #define CONFIG_ENV_SPI_MAX_HZ           10000000
  74 #define CONFIG_ENV_SPI_MODE             0
  75 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  76 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  77 #define CONFIG_ENV_SECT_SIZE            0x10000
  78 #elif defined(CONFIG_SDCARD)
  79 #define CONFIG_SYS_EXTRA_ENV_RELOC
  80 #define CONFIG_FSL_FIXED_MMC_LOCATION
  81 #define CONFIG_SYS_MMC_ENV_DEV          0
  82 #define CONFIG_ENV_SIZE                 0x2000
  83 #define CONFIG_ENV_OFFSET               (512 * 1658)
  84 #elif defined(CONFIG_NAND)
  85 #define CONFIG_SYS_EXTRA_ENV_RELOC
  86 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
  87 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  88 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  89 #define CONFIG_ENV_ADDR         0xffe20000
  90 #define CONFIG_ENV_SIZE         0x2000
  91 #elif defined(CONFIG_ENV_IS_NOWHERE)
  92 #define CONFIG_ENV_SIZE         0x2000
  93 #else
  94 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  95 #define CONFIG_ENV_SIZE         0x2000
  96 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
  97 #endif
  98
  99 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 100
 101 /*
 102  * These can be toggled for performance analysis, otherwise use default.
 103  */
 104 #define CONFIG_SYS_CACHE_STASHING
 105 #define CONFIG_BACKSIDE_L2_CACHE
 106 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 107 #define CONFIG_BTB                      /* toggle branch predition */
 108 #define CONFIG_DDR_ECC
 109 #ifdef CONFIG_DDR_ECC
 110 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 111 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 112 #endif
 113
 114 #define CONFIG_ENABLE_36BIT_PHYS
 115
 116 #ifdef CONFIG_PHYS_64BIT
 117 #define CONFIG_ADDR_MAP
 118 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 119 #endif
 120
 121 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 122 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 123 #define CONFIG_SYS_MEMTEST_END          0x00400000
 124
 125 /*
 126  *  Config the L3 Cache as L3 SRAM
 127  */
 128 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 129 #ifdef CONFIG_PHYS_64BIT
 130 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
 131 #else
 132 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 133 #endif
 134 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 135 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 136
 137 #ifdef CONFIG_PHYS_64BIT
 138 #define CONFIG_SYS_DCSRBAR              0xf0000000
 139 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 140 #endif
 141
 142 /* EEPROM */
 143 #define CONFIG_ID_EEPROM
 144 #define CONFIG_SYS_I2C_EEPROM_NXID
 145 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 146 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 147 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 148
 149 /*
 150  * DDR Setup
 151  */
 152 #define CONFIG_VERY_BIG_RAM
 153 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 154 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 155
 156 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 157 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 158
 159 #define CONFIG_DDR_SPD
 160
 161 #define CONFIG_SYS_SPD_BUS_NUM  1
 162 #define SPD_EEPROM_ADDRESS1     0x51
 163 #define SPD_EEPROM_ADDRESS2     0x52
 164 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 165 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 166
 167 /*
 168  * Local Bus Definitions
 169  */
 170
 171 /* Set the local bus clock 1/8 of platform clock */
 172 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 173
 174 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
 175 #ifdef CONFIG_PHYS_64BIT
 176 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 177 #else
 178 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 179 #endif
 180
 181 #define CONFIG_SYS_FLASH_BR_PRELIM \
 182                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
 183                  | BR_PS_16 | BR_V)
 184 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 185                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 186
 187 #define CONFIG_SYS_BR1_PRELIM \
 188         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 189 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 190
 191 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 192 #ifdef CONFIG_PHYS_64BIT
 193 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 194 #else
 195 #define PIXIS_BASE_PHYS         PIXIS_BASE
 196 #endif
 197
 198 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 199 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 200
 201 #define PIXIS_LBMAP_SWITCH      7
 202 #define PIXIS_LBMAP_MASK        0xf0
 203 #define PIXIS_LBMAP_SHIFT       4
 204 #define PIXIS_LBMAP_ALTBANK     0x40
 205
 206 #define CONFIG_SYS_FLASH_QUIET_TEST
 207 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 208
 209 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 210 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 211 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 212 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 213
 214 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 215
 216 #if defined(CONFIG_RAMBOOT_PBL)
 217 #define CONFIG_SYS_RAMBOOT
 218 #endif
 219
 220 /* Nand Flash */
 221 #ifdef CONFIG_NAND_FSL_ELBC
 222 #define CONFIG_SYS_NAND_BASE            0xffa00000
 223 #ifdef CONFIG_PHYS_64BIT
 224 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 225 #else
 226 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 227 #endif
 228
 229 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 230 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 231 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 232
 233 /* NAND flash config */
 234 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 235                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 236                                | BR_PS_8               /* Port Size = 8 bit */ \
 237                                | BR_MS_FCM             /* MSEL = FCM */ \
 238                                | BR_V)                 /* valid */
 239 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 240                                | OR_FCM_PGS            /* Large Page*/ \
 241                                | OR_FCM_CSCT \
 242                                | OR_FCM_CST \
 243                                | OR_FCM_CHT \
 244                                | OR_FCM_SCY_1 \
 245                                | OR_FCM_TRLX \
 246                                | OR_FCM_EHTR)
 247
 248 #ifdef CONFIG_NAND
 249 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 250 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 251 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 252 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 253 #else
 254 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 255 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 256 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 257 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 258 #endif
 259 #else
 260 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 261 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 262 #endif /* CONFIG_NAND_FSL_ELBC */
 263
 264 #define CONFIG_SYS_FLASH_EMPTY_INFO
 265 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 266 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 267
 268 #define CONFIG_MISC_INIT_R
 269
 270 #define CONFIG_HWCONFIG
 271
 272 /* define to use L1 as initial stack */
 273 #define CONFIG_L1_INIT_RAM
 274 #define CONFIG_SYS_INIT_RAM_LOCK
 275 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 276 #ifdef CONFIG_PHYS_64BIT
 277 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 278 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 279 /* The assembler doesn't like typecast */
 280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 281         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 282           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 283 #else
 284 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 285 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 286 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 287 #endif
 288 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 289
 290 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 291 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 292
 293 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 294 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 295
 296 /* Serial Port - controlled on board with jumper J8
 297  * open - index 2
 298  * shorted - index 1
 299  */
 300 #define CONFIG_SYS_NS16550_SERIAL
 301 #define CONFIG_SYS_NS16550_REG_SIZE     1
 302 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 303
 304 #define CONFIG_SYS_BAUDRATE_TABLE       \
 305         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 306
 307 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 308 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 309 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 310 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 311
 312 /* I2C */
 313 #define CONFIG_SYS_I2C
 314 #define CONFIG_SYS_I2C_FSL
 315 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 316 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 317 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 318 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 319 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 320 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 321
 322 /*
 323  * RapidIO
 324  */
 325 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 326 #ifdef CONFIG_PHYS_64BIT
 327 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 328 #else
 329 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 330 #endif
 331 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 332
 333 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 334 #ifdef CONFIG_PHYS_64BIT
 335 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 336 #else
 337 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 338 #endif
 339 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 340
 341 /*
 342  * for slave u-boot IMAGE instored in master memory space,
 343  * PHYS must be aligned based on the SIZE
 344  */
 345 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 346 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 347 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 348 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 349 /*
 350  * for slave UCODE and ENV instored in master memory space,
 351  * PHYS must be aligned based on the SIZE
 352  */
 353 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 354 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 355 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 356
 357 /* slave core release by master*/
 358 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 359 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 360
 361 /*
 362  * SRIO_PCIE_BOOT - SLAVE
 363  */
 364 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 365 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 366 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 367                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 368 #endif
 369
 370 /*
 371  * eSPI - Enhanced SPI
 372  */
 373 #define CONFIG_SF_DEFAULT_SPEED         10000000
 374 #define CONFIG_SF_DEFAULT_MODE          0
 375
 376 /*
 377  * General PCI
 378  * Memory space is mapped 1-1, but I/O space must start from 0.
 379  */
 380
 381 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 382 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 383 #ifdef CONFIG_PHYS_64BIT
 384 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 385 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 386 #else
 387 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 388 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 389 #endif
 390 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 391 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 392 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 393 #ifdef CONFIG_PHYS_64BIT
 394 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 395 #else
 396 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 397 #endif
 398 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 399
 400 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 401 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 402 #ifdef CONFIG_PHYS_64BIT
 403 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 404 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 405 #else
 406 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 407 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 408 #endif
 409 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 410 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 411 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 412 #ifdef CONFIG_PHYS_64BIT
 413 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 414 #else
 415 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 416 #endif
 417 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 418
 419 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 420 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 421 #ifdef CONFIG_PHYS_64BIT
 422 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 423 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 424 #else
 425 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 426 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 427 #endif
 428 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 429 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 430 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 431 #ifdef CONFIG_PHYS_64BIT
 432 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 433 #else
 434 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 435 #endif
 436 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 437
 438 /* controller 4, Base address 203000 */
 439 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 440 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 441 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 442 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 443 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 444 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 445
 446 /* Qman/Bman */
 447 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 448 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 449 #ifdef CONFIG_PHYS_64BIT
 450 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 451 #else
 452 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 453 #endif
 454 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 455 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 456 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 457 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 458 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 459 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 460                                         CONFIG_SYS_BMAN_CENA_SIZE)
 461 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 462 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 463 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 464 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 465 #ifdef CONFIG_PHYS_64BIT
 466 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 467 #else
 468 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 469 #endif
 470 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 471 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 472 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 473 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 474 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 475 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 476                                         CONFIG_SYS_QMAN_CENA_SIZE)
 477 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 478 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 479
 480 #define CONFIG_SYS_DPAA_FMAN
 481 #define CONFIG_SYS_DPAA_PME
 482 /* Default address of microcode for the Linux Fman driver */
 483 #if defined(CONFIG_SPIFLASH)
 484 /*
 485  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 486  * env, so we got 0x110000.
 487  */
 488 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 489 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 490 #elif defined(CONFIG_SDCARD)
 491 /*
 492  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 493  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 494  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 495  */
 496 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 497 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 498 #elif defined(CONFIG_NAND)
 499 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 500 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 501 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 502 /*
 503  * Slave has no ucode locally, it can fetch this from remote. When implementing
 504  * in two corenet boards, slave's ucode could be stored in master's memory
 505  * space, the address can be mapped from slave TLB->slave LAW->
 506  * slave SRIO or PCIE outbound window->master inbound window->
 507  * master LAW->the ucode address in master's memory space.
 508  */
 509 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 510 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 511 #else
 512 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 513 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 514 #endif
 515 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 516 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 517
 518 #ifdef CONFIG_SYS_DPAA_FMAN
 519 #define CONFIG_FMAN_ENET
 520 #define CONFIG_PHYLIB_10G
 521 #define CONFIG_PHY_VITESSE
 522 #define CONFIG_PHY_TERANETICS
 523 #endif
 524
 525 #ifdef CONFIG_PCI
 526 #define CONFIG_PCI_INDIRECT_BRIDGE
 527
 528 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 529 #endif  /* CONFIG_PCI */
 530
 531 /* SATA */
 532 #ifdef CONFIG_FSL_SATA_V2
 533 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 534 #define CONFIG_SATA1
 535 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 536 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 537 #define CONFIG_SATA2
 538 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 539 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 540
 541 #define CONFIG_LBA48
 542 #endif
 543
 544 #ifdef CONFIG_FMAN_ENET
 545 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 546 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 547 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 548 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 549 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 550
 551 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 552 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 553 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 554 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 555 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 556
 557 #define CONFIG_SYS_TBIPA_VALUE  8
 558 #define CONFIG_MII              /* MII PHY management */
 559 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 560 #endif
 561
 562 /*
 563  * Environment
 564  */
 565 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 566 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 567
 568 /*
 569 * USB
 570 */
 571 #define CONFIG_HAS_FSL_DR_USB
 572 #define CONFIG_HAS_FSL_MPH_USB
 573
 574 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 575 #define CONFIG_USB_EHCI_FSL
 576 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 577 #endif
 578
 579 #ifdef CONFIG_MMC
 580 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 581 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 582 #endif
 583
 584 /*
 585  * Miscellaneous configurable options
 586  */
 587 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 588
 589 /*
 590  * For booting Linux, the board info and command line data
 591  * have to be in the first 64 MB of memory, since this is
 592  * the maximum mapped by the Linux kernel during initialization.
 593  */
 594 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 595 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 596
 597 #ifdef CONFIG_CMD_KGDB
 598 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 599 #endif
 600
 601 /*
 602  * Environment Configuration
 603  */
 604 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 605 #define CONFIG_BOOTFILE         "uImage"
 606 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 607
 608 /* default location for tftp and bootm */
 609 #define CONFIG_LOADADDR         1000000
 610
 611 #ifdef CONFIG_TARGET_P4080DS
 612 #define __USB_PHY_TYPE  ulpi
 613 #else
 614 #define __USB_PHY_TYPE  utmi
 615 #endif
 616
 617 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 618         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 619         "bank_intlv=cs0_cs1;"                                   \
 620         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 621         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 622         "netdev=eth0\0"                                         \
 623         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 624         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 625         "tftpflash=tftpboot $loadaddr $uboot && "               \
 626         "protect off $ubootaddr +$filesize && "                 \
 627         "erase $ubootaddr +$filesize && "                       \
 628         "cp.b $loadaddr $ubootaddr $filesize && "               \
 629         "protect on $ubootaddr +$filesize && "                  \
 630         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 631         "consoledev=ttyS0\0"                                    \
 632         "ramdiskaddr=2000000\0"                                 \
 633         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 634         "fdtaddr=1e00000\0"                                     \
 635         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 636         "bdev=sda3\0"
 637
 638 #define CONFIG_HDBOOT                                   \
 639         "setenv bootargs root=/dev/$bdev rw "           \
 640         "console=$consoledev,$baudrate $othbootargs;"   \
 641         "tftp $loadaddr $bootfile;"                     \
 642         "tftp $fdtaddr $fdtfile;"                       \
 643         "bootm $loadaddr - $fdtaddr"
 644
 645 #define CONFIG_NFSBOOTCOMMAND                   \
 646         "setenv bootargs root=/dev/nfs rw "     \
 647         "nfsroot=$serverip:$rootpath "          \
 648         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 649         "console=$consoledev,$baudrate $othbootargs;"   \
 650         "tftp $loadaddr $bootfile;"             \
 651         "tftp $fdtaddr $fdtfile;"               \
 652         "bootm $loadaddr - $fdtaddr"
 653
 654 #define CONFIG_RAMBOOTCOMMAND                           \
 655         "setenv bootargs root=/dev/ram rw "             \
 656         "console=$consoledev,$baudrate $othbootargs;"   \
 657         "tftp $ramdiskaddr $ramdiskfile;"               \
 658         "tftp $loadaddr $bootfile;"                     \
 659         "tftp $fdtaddr $fdtfile;"                       \
 660         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 661
 662 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 663
 664 #include <asm/fsl_secure_boot.h>
 665
 666 #endif  /* __CONFIG_H */