3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Config header file for Cogent platform using an MPC8xx CPU module
32 * High Level Configuration Options
36 #define CONFIG_MPC860 1 /* This is an MPC860 CPU */
37 #define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
39 /* Cogent Modular Architecture options */
40 #define CONFIG_CMA286_60_OLD 1 /* ...on an old CMA286-60 CPU module */
41 #define CONFIG_CMA102 1 /* ...on a CMA102 motherboard */
42 #define CONFIG_CMA302 1 /* ...with a CMA302 flash I/O module */
44 /* serial console configuration */
45 #undef CONFIG_8xx_CONS_SMC1
46 #undef CONFIG_8xx_CONS_SMC2
47 #define CONFIG_8xx_CONS_NONE /* not on 8xx serial ports (eg on cogent m/b) */
49 #if defined(CONFIG_CMA286_60_OLD)
50 #define CONFIG_8xx_GCLK_FREQ 33333000 /* define if cant use get_gclk_freq */
53 #define CONFIG_BAUDRATE 230400
55 #define CONFIG_HARD_I2C /* I2C with hardware support */
56 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
57 #define CFG_I2C_SLAVE 0x7F
60 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_KGDB | CFG_CMD_I2C) & ~CFG_CMD_NET)
62 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
63 #include <cmd_confdefs.h>
66 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
68 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
70 #define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
72 #define CONFIG_BOOTARGS "root=/dev/ram rw"
74 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
75 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
76 #undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
77 #define CONFIG_KGDB_NONE /* define if kgdb on something else */
78 #define CONFIG_KGDB_INDEX 2 /* which SMC/SCC channel for kgdb */
79 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
82 #define CONFIG_WATCHDOG /* turn on platform specific watchdog */
85 * Miscellaneous configurable options
87 #define CFG_LONGHELP /* undef to save memory */
88 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
89 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
90 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
92 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
94 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
95 #define CFG_MAXARGS 16 /* max number of command args */
96 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
98 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
99 #define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
101 #define CFG_LOAD_ADDR 0x100000 /* default load address */
103 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
105 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
107 #define CFG_ALLOC_DPRAM
110 * Low Level Configuration Settings
111 * (address mappings, register initial values, etc.)
112 * You should know what you are doing if you make changes here.
115 /*-----------------------------------------------------------------------
116 * Low Level Cogent settings
117 * if CFG_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
118 * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
119 * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
120 * (second 2 for CMA120 only)
122 #define CFG_CMA_MB_BASE 0x00000000 /* base of m/b address space */
124 #include <configs/cogent_common.h>
126 #define CFG_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
127 #define CONFIG_CONS_INDEX 1
128 #define CFG_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
129 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
131 * flash exists on the motherboard
132 * set these four according to TOP dipsw:
133 * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
134 * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
136 #define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
137 #define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
138 #define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
139 #define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
141 #define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
142 #define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
144 /*-----------------------------------------------------------------------
145 * Internal Memory Mapped Register
147 #define CFG_IMMR 0xFF000000
149 /*-----------------------------------------------------------------------
150 * Definitions for initial stack pointer and data area (in DPRAM)
152 #define CFG_INIT_RAM_ADDR CFG_IMMR
153 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
154 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
155 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
156 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
158 /*-----------------------------------------------------------------------
159 * Start addresses for the final memory configuration
160 * (Set up by the startup code)
161 * Please note that CFG_SDRAM_BASE _must_ start at 0
163 #define CFG_SDRAM_BASE CMA_MB_RAM_BASE
165 #define CFG_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
167 #define CFG_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
169 #define CFG_MONITOR_BASE TEXT_BASE
170 #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
171 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
174 * For booting Linux, the board info and command line data
175 * have to be in the first 8 MB of memory, since this is
176 * the maximum mapped by the Linux kernel during initialization.
178 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
179 /*-----------------------------------------------------------------------
182 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
183 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
185 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
186 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
188 #define CFG_ENV_IS_IN_FLASH 1
189 #define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */
191 #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
192 #define CFG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
194 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
196 /*-----------------------------------------------------------------------
197 * Cache Configuration
199 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
200 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
201 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
205 /*-----------------------------------------------------------------------
206 * SYPCR - System Protection Control 11-9
207 * SYPCR can only be written once after reset!
208 *-----------------------------------------------------------------------
209 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
211 #if defined(CONFIG_WATCHDOG)
212 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
213 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
215 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
216 #endif /* CONFIG_WATCHDOG */
218 /*-----------------------------------------------------------------------
219 * SIUMCR - SIU Module Configuration 11-6
220 *-----------------------------------------------------------------------
221 * PCMCIA config., multi-function pin tri-state
223 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
225 /*-----------------------------------------------------------------------
226 * TBSCR - Time Base Status and Control 11-26
227 *-----------------------------------------------------------------------
228 * Clear Reference Interrupt Status, Timebase freezing enabled
230 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
232 /*-----------------------------------------------------------------------
233 * PISCR - Periodic Interrupt Status and Control 11-31
234 *-----------------------------------------------------------------------
235 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
237 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
239 /*-----------------------------------------------------------------------
240 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
241 *-----------------------------------------------------------------------
242 * Reset PLL lock status sticky bit, timer expired status bit and timer
243 * interrupt status bit - leave PLL multiplication factor unchanged !
245 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
247 /*-----------------------------------------------------------------------
248 * SCCR - System Clock and reset Control Register 15-27
249 *-----------------------------------------------------------------------
250 * Set clock output, timebase and RTC source and divider,
251 * power management and some other internal clocks
253 #define SCCR_MASK SCCR_EBDF11
254 #define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
255 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
256 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
259 /*-----------------------------------------------------------------------
261 *-----------------------------------------------------------------------
264 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
265 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
266 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
267 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
268 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
269 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
270 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
271 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
273 /*-----------------------------------------------------------------------
275 *-----------------------------------------------------------------------
278 /*#define CFG_DER 0x2002000F*/
281 #if defined(CONFIG_CMA286_60_OLD)
284 * Init Memory Controller:
286 * NOTE: although the names (CFG_xRn_PRELIM) suggest preliminary settings,
287 * they are actually the final settings for this cpu/board, because the
288 * flash and RAM are on the motherboard, accessed via the CMAbus, and the
289 * mappings are pretty much fixed.
291 * (the *_SIZE vars must be a power of 2)
294 #define CFG_CMA_CS0_BASE TEXT_BASE /* EPROM */
295 #define CFG_CMA_CS0_SIZE (1 << 20)
296 #define CFG_CMA_CS1_BASE CMA_MB_RAM_BASE /* RAM + I/O SLOT 1 */
297 #define CFG_CMA_CS1_SIZE (64 << 20)
298 #define CFG_CMA_CS2_BASE CMA_MB_SLOT2_BASE /* I/O SLOTS 2 + 3 */
299 #define CFG_CMA_CS2_SIZE (64 << 20)
300 #define CFG_CMA_CS3_BASE CMA_MB_ROMLOW_BASE /* M/B I/O */
301 #define CFG_CMA_CS3_SIZE (32 << 20)
304 * CS0 maps the EPROM on the cpu module
305 * Set it for 4 wait states, address CFG_MONITOR_BASE and size 1M
307 * Note: We must have already transferred control to the final location
308 * of the EPROM before these are used, because when BR0/OR0 are set, the
309 * mirror of the eprom at any other addresses will disappear.
312 /* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
313 #define CFG_BR0_PRELIM ((CFG_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
314 /* mask size CFG_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
315 #define CFG_OR0_PRELIM ((~(CFG_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)
318 * CS1 maps motherboard DRAM and motherboard I/O slot 1
319 * (each 32Mbyte in size)
322 /* base address = CFG_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
323 #define CFG_BR1_PRELIM ((CFG_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
324 /* mask size CFG_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
325 #define CFG_OR1_PRELIM ((~(CFG_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)
328 * CS2 maps motherboard I/O slots 2 and 3
329 * (each 32Mbyte in size)
332 /* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
333 #define CFG_BR2_PRELIM ((CFG_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
334 /* mask size CFG_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
335 #define CFG_OR2_PRELIM ((~(CFG_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)
338 * CS3 maps motherboard I/O
342 /* base address = CFG_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
343 #define CFG_BR3_PRELIM ((CFG_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
344 /* mask size CFG_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
345 #define CFG_OR3_PRELIM ((~(CFG_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
350 * Internal Definitions
354 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
355 #define BOOTFLAG_WARM 0x02 /* Software reboot */
357 #endif /* __CONFIG_H */