2 * (C) Copyright 2011 CompuLab, Ltd.
3 * Mike Rapoport <mike@compulab.co.il>
4 * Igor Grinberg <grinberg@compulab.co.il>
6 * Based on omap3_beagle.h
7 * (C) Copyright 2006-2008
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <x0khasim@ti.com>
12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
14 * SPDX-License-Identifier: GPL-2.0+
21 * High Level Configuration Options
23 #define CONFIG_OMAP /* in a TI OMAP core */
24 #define CONFIG_OMAP_GPIO
25 #define CONFIG_CMD_GPIO
26 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
27 #define CONFIG_OMAP_COMMON
28 #define CONFIG_SYS_GENERIC_BOARD
29 /* Common ARM Erratas */
30 #define CONFIG_ARM_ERRATA_454179
31 #define CONFIG_ARM_ERRATA_430973
32 #define CONFIG_ARM_ERRATA_621766
34 #define CONFIG_SDRC /* The chip has SDRC controller */
36 #include <asm/arch/cpu.h> /* get chip and board defs */
37 #include <asm/arch/omap.h>
40 * Display CPU and Board information
42 #define CONFIG_DISPLAY_CPUINFO
43 #define CONFIG_DISPLAY_BOARDINFO
46 #define V_OSCK 26000000 /* Clock output from T2 */
47 #define V_SCLK (V_OSCK >> 1)
49 #define CONFIG_MISC_INIT_R
51 #define CONFIG_OF_LIBFDT 1
53 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
54 #define CONFIG_SETUP_MEMORY_TAGS
55 #define CONFIG_INITRD_TAG
56 #define CONFIG_REVISION_TAG
57 #define CONFIG_SERIAL_TAG
60 * Size of malloc() pool
62 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
64 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
71 * NS16550 Configuration
73 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
75 #define CONFIG_SYS_NS16550
76 #define CONFIG_SYS_NS16550_SERIAL
77 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
78 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
81 * select serial console configuration
83 #define CONFIG_CONS_INDEX 3
84 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
85 #define CONFIG_SERIAL3 3 /* UART3 */
87 /* allow to overwrite serial and ethaddr */
88 #define CONFIG_ENV_OVERWRITE
89 #define CONFIG_BAUDRATE 115200
90 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
93 #define CONFIG_GENERIC_MMC
95 #define CONFIG_OMAP_HSMMC
96 #define CONFIG_DOS_PARTITION
99 #define CONFIG_USB_OMAP3
100 #define CONFIG_USB_EHCI
101 #define CONFIG_USB_EHCI_OMAP
102 #define CONFIG_USB_STORAGE
103 #define CONFIG_USB_MUSB_UDC
104 #define CONFIG_TWL4030_USB
105 #define CONFIG_CMD_USB
107 /* USB device configuration */
108 #define CONFIG_USB_DEVICE
109 #define CONFIG_USB_TTY
110 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
112 /* commands to include */
113 #define CONFIG_CMD_CACHE
114 #define CONFIG_CMD_EXT2 /* EXT2 Support */
115 #define CONFIG_CMD_FAT /* FAT support */
116 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
117 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
118 #define CONFIG_MTD_PARTITIONS
119 #define MTDIDS_DEFAULT "nand0=nand"
120 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
121 "1920k(u-boot),256k(u-boot-env),"\
124 #define CONFIG_CMD_I2C /* I2C serial bus support */
125 #define CONFIG_CMD_MMC /* MMC support */
126 #define CONFIG_CMD_NAND /* NAND support */
127 #define CONFIG_CMD_DHCP
128 #define CONFIG_CMD_PING
131 #define CONFIG_SYS_NO_FLASH
132 #define CONFIG_SYS_I2C
133 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
134 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
135 #define CONFIG_SYS_I2C_OMAP34XX
136 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
137 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
138 #define CONFIG_SYS_I2C_EEPROM_BUS 0
139 #define CONFIG_I2C_MULTI_BUS
144 #define CONFIG_TWL4030_POWER
145 #define CONFIG_TWL4030_LED
150 #define CONFIG_NAND_OMAP_GPMC
151 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
153 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
154 /* to access nand at */
156 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
159 /* Environment information */
160 #define CONFIG_BOOTDELAY 3
161 #define CONFIG_ZERO_BOOTDELAY_CHECK
163 #define CONFIG_EXTRA_ENV_SETTINGS \
164 "loadaddr=0x82000000\0" \
166 "console=ttyO2,115200n8\0" \
169 "dvimode=1024x768MR-16@60\0" \
170 "defaultdisplay=dvi\0" \
172 "mmcroot=/dev/mmcblk0p2 rw\0" \
173 "mmcrootfstype=ext4 rootwait\0" \
174 "nandroot=/dev/mtdblock4 rw\0" \
175 "nandrootfstype=ubifs\0" \
176 "mmcargs=setenv bootargs console=${console} " \
177 "mpurate=${mpurate} " \
179 "omapfb.mode=dvi:${dvimode} " \
180 "omapdss.def_disp=${defaultdisplay} " \
182 "rootfstype=${mmcrootfstype}\0" \
183 "nandargs=setenv bootargs console=${console} " \
184 "mpurate=${mpurate} " \
186 "omapfb.mode=dvi:${dvimode} " \
187 "omapdss.def_disp=${defaultdisplay} " \
188 "root=${nandroot} " \
189 "rootfstype=${nandrootfstype}\0" \
190 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
191 "bootscript=echo Running bootscript from mmc ...; " \
192 "source ${loadaddr}\0" \
193 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
194 "mmcboot=echo Booting from mmc ...; " \
196 "bootm ${loadaddr}\0" \
197 "nandboot=echo Booting from nand ...; " \
199 "nand read ${loadaddr} 2a0000 400000; " \
200 "bootm ${loadaddr}\0" \
202 #define CONFIG_CMD_BOOTZ
203 #define CONFIG_BOOTCOMMAND \
204 "mmc dev ${mmcdev}; if mmc rescan; then " \
205 "if run loadbootscript; then " \
208 "if run loaduimage; then " \
210 "else run nandboot; " \
213 "else run nandboot; fi"
216 * Miscellaneous configurable options
218 #define CONFIG_AUTO_COMPLETE
219 #define CONFIG_CMDLINE_EDITING
220 #define CONFIG_TIMESTAMP
221 #define CONFIG_SYS_AUTOLOAD "no"
222 #define CONFIG_SYS_LONGHELP /* undef to save memory */
223 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
224 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
225 /* Print Buffer Size */
226 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
227 sizeof(CONFIG_SYS_PROMPT) + 16)
228 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
229 /* Boot Argument Buffer Size */
230 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
232 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
234 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
235 0x01F00000) /* 31MB */
237 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
241 * OMAP3 has 12 GP timers, they can be driven by the system clock
242 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
243 * This rate is divided by a local divisor.
245 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
246 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
248 /*-----------------------------------------------------------------------
249 * Physical Memory Map
251 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
252 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
254 /*-----------------------------------------------------------------------
255 * FLASH and environment organization
258 /* **** PISMO SUPPORT *** */
259 /* Monitor at start of flash */
260 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
261 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
263 #define CONFIG_ENV_IS_IN_NAND
264 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
265 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
266 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
268 #if defined(CONFIG_CMD_NET)
269 #define CONFIG_SMC911X
270 #define CONFIG_SMC911X_32_BIT
271 #define CM_T3X_SMC911X_BASE 0x2C000000
272 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20))
273 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE
274 #endif /* (CONFIG_CMD_NET) */
276 /* additions for new relocation code, must be added to all boards */
277 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
278 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
279 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
280 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
281 CONFIG_SYS_INIT_RAM_SIZE - \
282 GENERATED_GBL_DATA_SIZE)
285 #define CONFIG_STATUS_LED /* Status LED enabled */
286 #define CONFIG_BOARD_SPECIFIC_LED
287 #define CONFIG_GPIO_LED
288 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
289 #define GREEN_LED_DEV 0
290 #define STATUS_LED_BIT GREEN_LED_GPIO
291 #define STATUS_LED_STATE STATUS_LED_ON
292 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
293 #define STATUS_LED_BOOT GREEN_LED_DEV
295 #define CONFIG_SPLASHIMAGE_GUARD
298 #ifdef CONFIG_STATUS_LED
299 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
302 /* Display Configuration */
303 #define CONFIG_OMAP3_GPIO_2
304 #define CONFIG_OMAP3_GPIO_5
305 #define CONFIG_VIDEO_OMAP3
306 #define LCD_BPP LCD_COLOR16
309 #define CONFIG_SPLASH_SCREEN
310 #define CONFIG_SPLASH_SOURCE
311 #define CONFIG_CMD_BMP
312 #define CONFIG_BMP_16BPP
313 #define CONFIG_SCF0403_LCD
315 #define CONFIG_OMAP3_SPI
317 /* Defines for SPL */
318 #define CONFIG_SPL_FRAMEWORK
319 #define CONFIG_SPL_NAND_SIMPLE
321 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
322 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
323 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
324 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
326 #define CONFIG_SPL_BOARD_INIT
327 #define CONFIG_SPL_LIBCOMMON_SUPPORT
328 #define CONFIG_SPL_LIBDISK_SUPPORT
329 #define CONFIG_SPL_I2C_SUPPORT
330 #define CONFIG_SPL_LIBGENERIC_SUPPORT
331 #define CONFIG_SPL_MMC_SUPPORT
332 #define CONFIG_SPL_FAT_SUPPORT
333 #define CONFIG_SPL_SERIAL_SUPPORT
334 #define CONFIG_SPL_NAND_SUPPORT
335 #define CONFIG_SPL_NAND_BASE
336 #define CONFIG_SPL_NAND_DRIVERS
337 #define CONFIG_SPL_NAND_ECC
338 #define CONFIG_SPL_GPIO_SUPPORT
339 #define CONFIG_SPL_POWER_SUPPORT
340 #define CONFIG_SPL_OMAP3_ID_NAND
341 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
343 /* NAND boot config */
344 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
345 #define CONFIG_SYS_NAND_PAGE_COUNT 64
346 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
347 #define CONFIG_SYS_NAND_OOBSIZE 64
348 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
349 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
351 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
352 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
354 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
356 #define CONFIG_SYS_NAND_ECCSIZE 512
357 #define CONFIG_SYS_NAND_ECCBYTES 3
358 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
360 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
361 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
363 #define CONFIG_SPL_TEXT_BASE 0x40200800
364 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
367 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
368 * older x-loader implementations. And move the BSS area so that it
369 * doesn't overlap with TEXT_BASE.
371 #define CONFIG_SYS_TEXT_BASE 0x80008000
372 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
373 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
375 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
376 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
378 #endif /* __CONFIG_H */