2 * (C) Copyright 2011 CompuLab, Ltd.
3 * Mike Rapoport <mike@compulab.co.il>
4 * Igor Grinberg <grinberg@compulab.co.il>
6 * Based on omap3_beagle.h
7 * (C) Copyright 2006-2008
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <x0khasim@ti.com>
12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
14 * SPDX-License-Identifier: GPL-2.0+
20 #define CONFIG_SYS_CACHELINE_SIZE 64
23 * High Level Configuration Options
25 #define CONFIG_OMAP /* in a TI OMAP core */
26 #define CONFIG_OMAP_GPIO
27 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
28 /* Common ARM Erratas */
29 #define CONFIG_ARM_ERRATA_454179
30 #define CONFIG_ARM_ERRATA_430973
31 #define CONFIG_ARM_ERRATA_621766
33 #define CONFIG_SDRC /* The chip has SDRC controller */
35 #include <asm/arch/cpu.h> /* get chip and board defs */
36 #include <asm/arch/omap.h>
39 #define V_OSCK 26000000 /* Clock output from T2 */
40 #define V_SCLK (V_OSCK >> 1)
42 #define CONFIG_MISC_INIT_R
44 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
45 #define CONFIG_SETUP_MEMORY_TAGS
46 #define CONFIG_INITRD_TAG
47 #define CONFIG_REVISION_TAG
48 #define CONFIG_SERIAL_TAG
51 * Size of malloc() pool
53 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
55 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
62 * NS16550 Configuration
64 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
66 #define CONFIG_SYS_NS16550_SERIAL
67 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
68 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
71 * select serial console configuration
73 #define CONFIG_CONS_INDEX 3
74 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
75 #define CONFIG_SERIAL3 3 /* UART3 */
77 /* allow to overwrite serial and ethaddr */
78 #define CONFIG_ENV_OVERWRITE
79 #define CONFIG_BAUDRATE 115200
80 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
83 #define CONFIG_GENERIC_MMC
85 #define CONFIG_OMAP_HSMMC
86 #define CONFIG_DOS_PARTITION
89 #define CONFIG_USB_OMAP3
90 #define CONFIG_USB_EHCI
91 #define CONFIG_USB_EHCI_OMAP
92 #define CONFIG_USB_MUSB_UDC
93 #define CONFIG_TWL4030_USB
95 /* USB device configuration */
96 #define CONFIG_USB_DEVICE
97 #define CONFIG_USB_TTY
99 /* commands to include */
100 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
101 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
102 #define CONFIG_MTD_PARTITIONS
103 #define MTDIDS_DEFAULT "nand0=nand"
104 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
105 "1920k(u-boot),256k(u-boot-env),"\
108 #define CONFIG_CMD_NAND /* NAND support */
110 #define CONFIG_SYS_NO_FLASH
111 #define CONFIG_SYS_I2C
112 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
113 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
114 #define CONFIG_SYS_I2C_OMAP34XX
115 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
116 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
117 #define CONFIG_SYS_I2C_EEPROM_BUS 0
118 #define CONFIG_I2C_MULTI_BUS
123 #define CONFIG_TWL4030_POWER
124 #define CONFIG_TWL4030_LED
129 #define CONFIG_NAND_OMAP_GPMC
130 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
132 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
133 /* to access nand at */
135 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
138 /* Environment information */
139 #define CONFIG_EXTRA_ENV_SETTINGS \
140 "loadaddr=0x82000000\0" \
142 "console=ttyO2,115200n8\0" \
145 "dvimode=1024x768MR-16@60\0" \
146 "defaultdisplay=dvi\0" \
148 "mmcroot=/dev/mmcblk0p2 rw\0" \
149 "mmcrootfstype=ext4 rootwait\0" \
150 "nandroot=/dev/mtdblock4 rw\0" \
151 "nandrootfstype=ubifs\0" \
152 "mmcargs=setenv bootargs console=${console} " \
153 "mpurate=${mpurate} " \
155 "omapfb.mode=dvi:${dvimode} " \
156 "omapdss.def_disp=${defaultdisplay} " \
158 "rootfstype=${mmcrootfstype}\0" \
159 "nandargs=setenv bootargs console=${console} " \
160 "mpurate=${mpurate} " \
162 "omapfb.mode=dvi:${dvimode} " \
163 "omapdss.def_disp=${defaultdisplay} " \
164 "root=${nandroot} " \
165 "rootfstype=${nandrootfstype}\0" \
166 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
167 "bootscript=echo Running bootscript from mmc ...; " \
168 "source ${loadaddr}\0" \
169 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
170 "mmcboot=echo Booting from mmc ...; " \
172 "bootm ${loadaddr}\0" \
173 "nandboot=echo Booting from nand ...; " \
175 "nand read ${loadaddr} 2a0000 400000; " \
176 "bootm ${loadaddr}\0" \
178 #define CONFIG_BOOTCOMMAND \
179 "mmc dev ${mmcdev}; if mmc rescan; then " \
180 "if run loadbootscript; then " \
183 "if run loaduimage; then " \
185 "else run nandboot; " \
188 "else run nandboot; fi"
191 * Miscellaneous configurable options
193 #define CONFIG_AUTO_COMPLETE
194 #define CONFIG_CMDLINE_EDITING
195 #define CONFIG_TIMESTAMP
196 #define CONFIG_SYS_AUTOLOAD "no"
197 #define CONFIG_SYS_LONGHELP /* undef to save memory */
198 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
199 /* Print Buffer Size */
200 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
201 sizeof(CONFIG_SYS_PROMPT) + 16)
202 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
203 /* Boot Argument Buffer Size */
204 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
206 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
208 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
209 0x01F00000) /* 31MB */
211 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
215 * OMAP3 has 12 GP timers, they can be driven by the system clock
216 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
217 * This rate is divided by a local divisor.
219 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
220 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
222 /*-----------------------------------------------------------------------
223 * Physical Memory Map
225 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
226 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
228 /*-----------------------------------------------------------------------
229 * FLASH and environment organization
232 /* **** PISMO SUPPORT *** */
233 /* Monitor at start of flash */
234 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
235 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
237 #define CONFIG_ENV_IS_IN_NAND
238 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
239 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
240 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
242 #if defined(CONFIG_CMD_NET)
243 #define CONFIG_SMC911X
244 #define CONFIG_SMC911X_32_BIT
245 #define CM_T3X_SMC911X_BASE 0x2C000000
246 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20))
247 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE
248 #endif /* (CONFIG_CMD_NET) */
250 /* additions for new relocation code, must be added to all boards */
251 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
252 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
253 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
254 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
255 CONFIG_SYS_INIT_RAM_SIZE - \
256 GENERATED_GBL_DATA_SIZE)
259 #define CONFIG_STATUS_LED /* Status LED enabled */
260 #define CONFIG_BOARD_SPECIFIC_LED
261 #define CONFIG_GPIO_LED
262 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
263 #define GREEN_LED_DEV 0
264 #define STATUS_LED_BIT GREEN_LED_GPIO
265 #define STATUS_LED_STATE STATUS_LED_ON
266 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
267 #define STATUS_LED_BOOT GREEN_LED_DEV
269 #define CONFIG_SPLASHIMAGE_GUARD
272 #ifdef CONFIG_STATUS_LED
273 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
276 /* Display Configuration */
277 #define CONFIG_OMAP3_GPIO_2
278 #define CONFIG_OMAP3_GPIO_5
279 #define CONFIG_VIDEO_OMAP3
280 #define LCD_BPP LCD_COLOR16
282 #define CONFIG_SPLASH_SCREEN
283 #define CONFIG_SPLASH_SOURCE
284 #define CONFIG_CMD_BMP
285 #define CONFIG_BMP_16BPP
286 #define CONFIG_SCF0403_LCD
288 #define CONFIG_OMAP3_SPI
290 /* Defines for SPL */
291 #define CONFIG_SPL_FRAMEWORK
292 #define CONFIG_SPL_NAND_SIMPLE
294 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
295 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
297 #define CONFIG_SPL_BOARD_INIT
298 #define CONFIG_SPL_NAND_BASE
299 #define CONFIG_SPL_NAND_DRIVERS
300 #define CONFIG_SPL_NAND_ECC
301 #define CONFIG_SPL_OMAP3_ID_NAND
302 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
304 /* NAND boot config */
305 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
306 #define CONFIG_SYS_NAND_PAGE_COUNT 64
307 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
308 #define CONFIG_SYS_NAND_OOBSIZE 64
309 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
310 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
312 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
313 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
315 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
317 #define CONFIG_SYS_NAND_ECCSIZE 512
318 #define CONFIG_SYS_NAND_ECCBYTES 3
319 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
321 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
322 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
324 #define CONFIG_SPL_TEXT_BASE 0x40200800
325 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
326 CONFIG_SPL_TEXT_BASE)
329 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
330 * older x-loader implementations. And move the BSS area so that it
331 * doesn't overlap with TEXT_BASE.
333 #define CONFIG_SYS_TEXT_BASE 0x80008000
334 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
335 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
337 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
338 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
341 #define CONFIG_CMD_EEPROM
342 #define CONFIG_ENV_EEPROM_IS_ON_I2C
343 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
344 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
345 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
346 #define CONFIG_SYS_EEPROM_SIZE 256
348 #define CONFIG_CMD_EEPROM_LAYOUT
349 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3"
351 #endif /* __CONFIG_H */