2 * (C) Copyright 2011 CompuLab, Ltd.
3 * Mike Rapoport <mike@compulab.co.il>
4 * Igor Grinberg <grinberg@compulab.co.il>
6 * Based on omap3_beagle.h
7 * (C) Copyright 2006-2008
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <x0khasim@ti.com>
12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
14 * SPDX-License-Identifier: GPL-2.0+
20 #define CONFIG_SYS_CACHELINE_SIZE 64
23 * High Level Configuration Options
25 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
27 #define CONFIG_SDRC /* The chip has SDRC controller */
29 #include <asm/arch/cpu.h> /* get chip and board defs */
30 #include <asm/arch/omap.h>
33 #define V_OSCK 26000000 /* Clock output from T2 */
34 #define V_SCLK (V_OSCK >> 1)
36 #define CONFIG_MISC_INIT_R
38 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
39 #define CONFIG_SETUP_MEMORY_TAGS
40 #define CONFIG_INITRD_TAG
41 #define CONFIG_REVISION_TAG
42 #define CONFIG_SERIAL_TAG
45 * Size of malloc() pool
47 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
49 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
56 * NS16550 Configuration
58 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
60 #define CONFIG_SYS_NS16550_SERIAL
61 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
62 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
65 * select serial console configuration
67 #define CONFIG_CONS_INDEX 3
68 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
69 #define CONFIG_SERIAL3 3 /* UART3 */
71 /* allow to overwrite serial and ethaddr */
72 #define CONFIG_ENV_OVERWRITE
73 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
77 #define CONFIG_USB_OMAP3
78 #define CONFIG_USB_MUSB_UDC
79 #define CONFIG_TWL4030_USB
81 /* USB device configuration */
82 #define CONFIG_USB_DEVICE
83 #define CONFIG_USB_TTY
85 /* commands to include */
86 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
87 #define CONFIG_MTD_PARTITIONS
88 #define MTDIDS_DEFAULT "nand0=nand"
89 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
90 "1920k(u-boot),256k(u-boot-env),"\
93 #define CONFIG_SYS_I2C
94 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
95 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
96 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
97 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
98 #define CONFIG_SYS_I2C_EEPROM_BUS 0
99 #define CONFIG_I2C_MULTI_BUS
104 #define CONFIG_TWL4030_LED
109 #define CONFIG_NAND_OMAP_GPMC
110 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
112 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
113 /* to access nand at */
115 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
118 /* Environment information */
119 #define CONFIG_EXTRA_ENV_SETTINGS \
120 "loadaddr=0x82000000\0" \
122 "console=ttyO2,115200n8\0" \
125 "dvimode=1024x768MR-16@60\0" \
126 "defaultdisplay=dvi\0" \
128 "mmcroot=/dev/mmcblk0p2 rw\0" \
129 "mmcrootfstype=ext4 rootwait\0" \
130 "nandroot=/dev/mtdblock4 rw\0" \
131 "nandrootfstype=ubifs\0" \
132 "mmcargs=setenv bootargs console=${console} " \
133 "mpurate=${mpurate} " \
135 "omapfb.mode=dvi:${dvimode} " \
136 "omapdss.def_disp=${defaultdisplay} " \
138 "rootfstype=${mmcrootfstype}\0" \
139 "nandargs=setenv bootargs console=${console} " \
140 "mpurate=${mpurate} " \
142 "omapfb.mode=dvi:${dvimode} " \
143 "omapdss.def_disp=${defaultdisplay} " \
144 "root=${nandroot} " \
145 "rootfstype=${nandrootfstype}\0" \
146 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
147 "bootscript=echo Running bootscript from mmc ...; " \
148 "source ${loadaddr}\0" \
149 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
150 "mmcboot=echo Booting from mmc ...; " \
152 "bootm ${loadaddr}\0" \
153 "nandboot=echo Booting from nand ...; " \
155 "nand read ${loadaddr} 2a0000 400000; " \
156 "bootm ${loadaddr}\0" \
158 #define CONFIG_BOOTCOMMAND \
159 "mmc dev ${mmcdev}; if mmc rescan; then " \
160 "if run loadbootscript; then " \
163 "if run loaduimage; then " \
165 "else run nandboot; " \
168 "else run nandboot; fi"
171 * Miscellaneous configurable options
173 #define CONFIG_AUTO_COMPLETE
174 #define CONFIG_CMDLINE_EDITING
175 #define CONFIG_TIMESTAMP
176 #define CONFIG_SYS_AUTOLOAD "no"
177 #define CONFIG_SYS_LONGHELP /* undef to save memory */
178 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
179 /* Print Buffer Size */
180 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
181 sizeof(CONFIG_SYS_PROMPT) + 16)
182 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
183 /* Boot Argument Buffer Size */
184 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
186 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
188 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
189 0x01F00000) /* 31MB */
191 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
195 * OMAP3 has 12 GP timers, they can be driven by the system clock
196 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
197 * This rate is divided by a local divisor.
199 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
200 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
202 /*-----------------------------------------------------------------------
203 * Physical Memory Map
205 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
206 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
208 /*-----------------------------------------------------------------------
209 * FLASH and environment organization
212 /* **** PISMO SUPPORT *** */
213 /* Monitor at start of flash */
214 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
215 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
217 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
218 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
219 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
221 #if defined(CONFIG_CMD_NET)
222 #define CONFIG_SMC911X
223 #define CONFIG_SMC911X_32_BIT
224 #define CM_T3X_SMC911X_BASE 0x2C000000
225 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20))
226 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE
227 #endif /* (CONFIG_CMD_NET) */
229 /* additions for new relocation code, must be added to all boards */
230 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
231 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
232 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
233 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
234 CONFIG_SYS_INIT_RAM_SIZE - \
235 GENERATED_GBL_DATA_SIZE)
238 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
240 #define CONFIG_SPLASHIMAGE_GUARD
242 /* Display Configuration */
243 #define CONFIG_VIDEO_OMAP3
244 #define LCD_BPP LCD_COLOR16
246 #define CONFIG_SPLASH_SCREEN
247 #define CONFIG_SPLASH_SOURCE
248 #define CONFIG_BMP_16BPP
249 #define CONFIG_SCF0403_LCD
251 #define CONFIG_OMAP3_SPI
253 /* Defines for SPL */
254 #define CONFIG_SPL_FRAMEWORK
255 #define CONFIG_SPL_NAND_SIMPLE
257 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
258 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
260 #define CONFIG_SPL_NAND_BASE
261 #define CONFIG_SPL_NAND_DRIVERS
262 #define CONFIG_SPL_NAND_ECC
263 #define CONFIG_SPL_OMAP3_ID_NAND
265 /* NAND boot config */
266 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
267 #define CONFIG_SYS_NAND_PAGE_COUNT 64
268 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
269 #define CONFIG_SYS_NAND_OOBSIZE 64
270 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
271 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
273 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
274 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
276 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
278 #define CONFIG_SYS_NAND_ECCSIZE 512
279 #define CONFIG_SYS_NAND_ECCBYTES 3
280 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
282 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
283 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
285 #define CONFIG_SPL_TEXT_BASE 0x40200800
286 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
287 CONFIG_SPL_TEXT_BASE)
290 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
291 * older x-loader implementations. And move the BSS area so that it
292 * doesn't overlap with TEXT_BASE.
294 #define CONFIG_SYS_TEXT_BASE 0x80008000
295 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
296 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
298 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
299 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
302 #define CONFIG_ENV_EEPROM_IS_ON_I2C
303 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
304 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
305 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
306 #define CONFIG_SYS_EEPROM_SIZE 256
308 #endif /* __CONFIG_H */