2 * (C) Copyright 2011 CompuLab, Ltd.
3 * Mike Rapoport <mike@compulab.co.il>
4 * Igor Grinberg <grinberg@compulab.co.il>
6 * Based on omap3_beagle.h
7 * (C) Copyright 2006-2008
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <x0khasim@ti.com>
12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
36 * High Level Configuration Options
38 #define CONFIG_OMAP /* in a TI OMAP core */
39 #define CONFIG_OMAP34XX /* which is a 34XX */
40 #define CONFIG_OMAP_GPIO
41 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
43 #define CONFIG_SYS_TEXT_BASE 0x80008000
45 #define CONFIG_SDRC /* The chip has SDRC controller */
47 #include <asm/arch/cpu.h> /* get chip and board defs */
48 #include <asm/arch/omap3.h>
51 * Display CPU and Board information
53 #define CONFIG_DISPLAY_CPUINFO
54 #define CONFIG_DISPLAY_BOARDINFO
57 #define V_OSCK 26000000 /* Clock output from T2 */
58 #define V_SCLK (V_OSCK >> 1)
60 #undef CONFIG_USE_IRQ /* no support for IRQs */
61 #define CONFIG_MISC_INIT_R
63 #define CONFIG_OF_LIBFDT 1
65 * The early kernel mapping on ARM currently only maps from the base of DRAM
66 * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
67 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
68 * so that leaves DRAM base to DRAM base + 0x4000 available.
70 #define CONFIG_SYS_BOOTMAPSZ 0x4000
72 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
73 #define CONFIG_SETUP_MEMORY_TAGS
74 #define CONFIG_INITRD_TAG
75 #define CONFIG_REVISION_TAG
76 #define CONFIG_SERIAL_TAG
79 * Size of malloc() pool
81 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
83 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
90 * NS16550 Configuration
92 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
94 #define CONFIG_SYS_NS16550
95 #define CONFIG_SYS_NS16550_SERIAL
96 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
97 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
100 * select serial console configuration
102 #define CONFIG_CONS_INDEX 3
103 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
104 #define CONFIG_SERIAL3 3 /* UART3 */
106 /* allow to overwrite serial and ethaddr */
107 #define CONFIG_ENV_OVERWRITE
108 #define CONFIG_BAUDRATE 115200
109 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
112 #define CONFIG_GENERIC_MMC
114 #define CONFIG_OMAP_HSMMC
115 #define CONFIG_DOS_PARTITION
118 #define CONFIG_MUSB_UDC
119 #define CONFIG_USB_OMAP3
120 #define CONFIG_TWL4030_USB
122 /* USB device configuration */
123 #define CONFIG_USB_DEVICE
124 #define CONFIG_USB_TTY
125 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
127 /* commands to include */
128 #include <config_cmd_default.h>
130 #define CONFIG_CMD_CACHE
131 #define CONFIG_CMD_EXT2 /* EXT2 Support */
132 #define CONFIG_CMD_FAT /* FAT support */
133 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
134 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
135 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
136 #define MTDIDS_DEFAULT "nand0=nand"
137 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
138 "1920k(u-boot),128k(u-boot-env),"\
141 #define CONFIG_CMD_I2C /* I2C serial bus support */
142 #define CONFIG_CMD_MMC /* MMC support */
143 #define CONFIG_CMD_NAND /* NAND support */
144 #define CONFIG_CMD_DHCP
145 #define CONFIG_CMD_PING
147 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
148 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
149 #undef CONFIG_CMD_IMLS /* List all found images */
151 #define CONFIG_SYS_NO_FLASH
152 #define CONFIG_HARD_I2C
153 #define CONFIG_SYS_I2C_SPEED 100000
154 #define CONFIG_SYS_I2C_SLAVE 1
155 #define CONFIG_SYS_I2C_BUS 0
156 #define CONFIG_SYS_I2C_BUS_SELECT 1
157 #define CONFIG_DRIVER_OMAP34XX_I2C
158 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
159 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
160 #define CONFIG_I2C_MULTI_BUS
165 #define CONFIG_TWL4030_POWER
166 #define CONFIG_TWL4030_LED
171 #define CONFIG_SYS_NAND_QUIET_TEST
172 #define CONFIG_NAND_OMAP_GPMC
173 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
175 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
176 /* to access nand at */
178 #define GPMC_NAND_ECC_LP_x8_LAYOUT
180 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
182 #define CONFIG_JFFS2_NAND
183 /* nand device jffs2 lives on */
184 #define CONFIG_JFFS2_DEV "nand0"
185 /* start of jffs2 partition */
186 #define CONFIG_JFFS2_PART_OFFSET 0x680000
187 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
190 /* Environment information */
191 #define CONFIG_BOOTDELAY 10
193 #define CONFIG_EXTRA_ENV_SETTINGS \
194 "loadaddr=0x82000000\0" \
196 "console=ttyS2,115200n8\0" \
199 "dvimode=1024x768MR-16@60\0" \
200 "defaultdisplay=dvi\0" \
202 "mmcroot=/dev/mmcblk0p2 rw\0" \
203 "mmcrootfstype=ext3 rootwait\0" \
204 "nandroot=/dev/mtdblock4 rw\0" \
205 "nandrootfstype=jffs2\0" \
206 "mmcargs=setenv bootargs console=${console} " \
207 "mpurate=${mpurate} " \
209 "omapfb.mode=dvi:${dvimode} " \
211 "omapdss.def_disp=${defaultdisplay} " \
213 "rootfstype=${mmcrootfstype}\0" \
214 "nandargs=setenv bootargs console=${console} " \
215 "mpurate=${mpurate} " \
217 "omapfb.mode=dvi:${dvimode} " \
219 "omapdss.def_disp=${defaultdisplay} " \
220 "root=${nandroot} " \
221 "rootfstype=${nandrootfstype}\0" \
222 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
223 "bootscript=echo Running bootscript from mmc ...; " \
224 "source ${loadaddr}\0" \
225 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
226 "mmcboot=echo Booting from mmc ...; " \
228 "bootm ${loadaddr}\0" \
229 "nandboot=echo Booting from nand ...; " \
231 "nand read ${loadaddr} 280000 400000; " \
232 "bootm ${loadaddr}\0" \
234 #define CONFIG_BOOTCOMMAND \
235 "if mmc rescan ${mmcdev}; then " \
236 "if run loadbootscript; then " \
239 "if run loaduimage; then " \
241 "else run nandboot; " \
244 "else run nandboot; fi"
247 * Miscellaneous configurable options
249 #define CONFIG_AUTO_COMPLETE
250 #define CONFIG_CMDLINE_EDITING
251 #define CONFIG_TIMESTAMP
252 #define CONFIG_SYS_AUTOLOAD "no"
253 #define CONFIG_SYS_LONGHELP /* undef to save memory */
254 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
255 #define CONFIG_SYS_PROMPT "CM-T3x # "
256 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
257 /* Print Buffer Size */
258 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
259 sizeof(CONFIG_SYS_PROMPT) + 16)
260 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
261 /* Boot Argument Buffer Size */
262 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
264 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
266 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
267 0x01F00000) /* 31MB */
269 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
273 * OMAP3 has 12 GP timers, they can be driven by the system clock
274 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
275 * This rate is divided by a local divisor.
277 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
278 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
279 #define CONFIG_SYS_HZ 1000
281 /*-----------------------------------------------------------------------
284 * The stack sizes are set up in start.S using the settings below
286 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
288 /*-----------------------------------------------------------------------
289 * Physical Memory Map
291 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
292 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
293 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
295 /*-----------------------------------------------------------------------
296 * FLASH and environment organization
299 /* **** PISMO SUPPORT *** */
301 /* Configure the PISMO */
302 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
303 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
305 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
307 #if defined(CONFIG_CMD_NAND)
308 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
311 /* Monitor at start of flash */
312 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
313 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
315 #define CONFIG_ENV_IS_IN_NAND
316 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
317 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
319 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
320 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
322 #if defined(CONFIG_CMD_NET)
323 #define CONFIG_SMC911X
324 #define CONFIG_SMC911X_32_BIT
325 #define CM_T3X_SMC911X_BASE 0x2C000000
326 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20))
327 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE
328 #endif /* (CONFIG_CMD_NET) */
330 /* additions for new relocation code, must be added to all boards */
331 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
332 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
333 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
334 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
335 CONFIG_SYS_INIT_RAM_SIZE - \
336 GENERATED_GBL_DATA_SIZE)
339 #define CONFIG_STATUS_LED /* Status LED enabled */
340 #define CONFIG_BOARD_SPECIFIC_LED
341 #define STATUS_LED_GREEN 0
342 #define STATUS_LED_BIT STATUS_LED_GREEN
343 #define STATUS_LED_STATE STATUS_LED_ON
344 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
345 #define STATUS_LED_BOOT STATUS_LED_BIT
346 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
349 #ifdef CONFIG_STATUS_LED
350 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
353 #endif /* __CONFIG_H */