2 * Config file for Compulab CM-FX6 board
4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
6 * Author: Nikita Kiryanov <nikita@compulab.co.il>
8 * SPDX-License-Identifier: GPL-2.0+
11 #ifndef __CONFIG_CM_FX6_H
12 #define __CONFIG_CM_FX6_H
14 #include <asm/arch/imx-regs.h>
15 #include <config_distro_defaults.h>
16 #include "mx6_common.h"
20 #define CONFIG_SYS_LITTLE_ENDIAN
21 #define CONFIG_MACH_TYPE 4273
23 #ifndef CONFIG_SPL_BUILD
27 #define CONFIG_DM_GPIO
28 #define CONFIG_CMD_GPIO
30 #define CONFIG_DM_SERIAL
31 #define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
34 /* Display information on boot */
35 #define CONFIG_DISPLAY_CPUINFO
36 #define CONFIG_DISPLAY_BOARDINFO
37 #define CONFIG_TIMESTAMP
40 #include <config_cmd_default.h>
41 #define CONFIG_CMD_GREPENV
42 #undef CONFIG_CMD_FLASH
43 #undef CONFIG_CMD_LOADB
44 #undef CONFIG_CMD_LOADS
45 #undef CONFIG_CMD_XIMG
46 #undef CONFIG_CMD_FPGA
47 #undef CONFIG_CMD_IMLS
51 #define CONFIG_CMD_MMC
52 #define CONFIG_GENERIC_MMC
53 #define CONFIG_FSL_ESDHC
54 #define CONFIG_FSL_USDHC
55 #define CONFIG_SYS_FSL_USDHC_NUM 3
56 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
59 #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
60 #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR
61 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
62 #define CONFIG_NR_DRAM_BANKS 2
63 #define CONFIG_SYS_MEMTEST_START 0x10000000
64 #define CONFIG_SYS_MEMTEST_END 0x10010000
65 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
66 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
67 #define CONFIG_SYS_INIT_SP_OFFSET \
68 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
69 #define CONFIG_SYS_INIT_SP_ADDR \
70 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
73 #define CONFIG_MXC_UART
74 #define CONFIG_MXC_UART_BASE UART4_BASE
75 #define CONFIG_BAUDRATE 115200
76 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
79 #define CONFIG_SYS_PROMPT "CM-FX6 # "
80 #define CONFIG_SYS_CBSIZE 1024
81 #define CONFIG_SYS_MAXARGS 16
82 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
83 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
84 sizeof(CONFIG_SYS_PROMPT) + 16)
87 #define CONFIG_SYS_NO_FLASH
89 #define CONFIG_SF_DEFAULT_BUS 0
90 #define CONFIG_SF_DEFAULT_CS 0
91 #define CONFIG_SF_DEFAULT_SPEED 25000000
92 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
95 #define CONFIG_ENV_OVERWRITE
96 #define CONFIG_ENV_IS_IN_SPI_FLASH
97 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
98 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
99 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
100 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
101 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
102 #define CONFIG_ENV_SIZE (8 * 1024)
103 #define CONFIG_ENV_OFFSET (768 * 1024)
105 #define CONFIG_EXTRA_ENV_SETTINGS \
107 "kernel=uImage-cm-fx6\0" \
108 "script=boot.scr\0" \
110 "bootm_low=18000000\0" \
111 "loadaddr=0x10800000\0" \
112 "fdtaddr=0x11000000\0" \
113 "console=ttymxc3,115200\0" \
115 "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
116 "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
117 "doboot=bootm ${loadaddr}\0" \
118 "doloadfdt=false\0" \
119 "setboottypez=setenv kernel zImage-cm-fx6;" \
120 "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
121 "setenv doloadfdt true;\0" \
122 "setboottypem=setenv kernel uImage-cm-fx6;" \
123 "setenv doboot bootm ${loadaddr};" \
124 "setenv doloadfdt false;\0"\
125 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
126 "sataroot=/dev/sda2 rw rootwait\0" \
127 "nandroot=/dev/mtdblock4 rw\0" \
128 "nandrootfstype=ubifs\0" \
129 "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \
131 "sataargs=setenv bootargs console=${console} root=${sataroot} " \
133 "nandargs=setenv bootargs console=${console} " \
134 "root=${nandroot} " \
135 "rootfstype=${nandrootfstype} " \
137 "nandboot=if run nandloadkernel; then " \
139 "run setboottypem;" \
140 "run storagebootcmd;" \
141 "run setboottypez;" \
142 "run storagebootcmd;" \
144 "run_eboot=echo Starting EBOOT ...; "\
146 "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
147 "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0"\
148 "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0"\
149 "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${dtb};\0" \
150 "bootscript=echo Running bootscript from ${storagetype} ...;" \
151 "source ${loadaddr};\0" \
152 "nandloadkernel=nand read ${loadaddr} 0 780000;\0" \
153 "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \
154 "setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \
155 "setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \
156 "setupnandboot=setenv storagetype nand;\0" \
157 "setupusbboot=setenv storagetype usb; setenv storagedev 0;\0" \
158 "storagebootcmd=echo Booting from ${storagetype} ...;" \
159 "run ${storagetype}args; run doboot;\0" \
160 "trybootk=if run loadkernel; then " \
161 "if ${doloadfdt}; then " \
164 "run storagebootcmd;" \
166 "trybootsmz=if run loadscript; then " \
169 "run setboottypem;" \
171 "run setboottypez;" \
174 #define CONFIG_BOOTCOMMAND \
175 "run setupmmcboot;" \
176 "mmc dev ${storagedev};" \
177 "if mmc rescan; then " \
180 "run setupusbboot;" \
181 "if usb start; then "\
182 "if run loadscript; then " \
186 "run setupsataboot;" \
187 "if sata init; then " \
190 "run setupnandboot;" \
195 #define CONFIG_MXC_SPI
196 #define CONFIG_SPI_FLASH
197 #define CONFIG_SPI_FLASH_ATMEL
198 #define CONFIG_SPI_FLASH_EON
199 #define CONFIG_SPI_FLASH_GIGADEVICE
200 #define CONFIG_SPI_FLASH_MACRONIX
201 #define CONFIG_SPI_FLASH_SPANSION
202 #define CONFIG_SPI_FLASH_STMICRO
203 #define CONFIG_SPI_FLASH_SST
204 #define CONFIG_SPI_FLASH_WINBOND
207 #ifndef CONFIG_SPL_BUILD
208 #define CONFIG_CMD_NAND
209 #define CONFIG_SYS_NAND_BASE 0x40000000
210 #define CONFIG_SYS_NAND_MAX_CHIPS 1
211 #define CONFIG_SYS_MAX_NAND_DEVICE 1
212 #define CONFIG_NAND_MXS
213 #define CONFIG_SYS_NAND_ONFI_DETECTION
214 /* APBH DMA is required for NAND support */
215 #define CONFIG_APBH_DMA
216 #define CONFIG_APBH_DMA_BURST
217 #define CONFIG_APBH_DMA_BURST8
221 #define CONFIG_FEC_MXC
222 #define CONFIG_FEC_MXC_PHYADDR 0
223 #define CONFIG_FEC_XCV_TYPE RGMII
224 #define IMX_FEC_BASE ENET_BASE_ADDR
225 #define CONFIG_PHYLIB
226 #define CONFIG_PHY_ATHEROS
228 #define CONFIG_ETHPRIME "FEC0"
229 #define CONFIG_ARP_TIMEOUT 200UL
230 #define CONFIG_NET_RETRY_COUNT 5
233 #define CONFIG_CMD_USB
234 #define CONFIG_USB_EHCI
235 #define CONFIG_USB_EHCI_MX6
236 #define CONFIG_USB_STORAGE
237 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
238 #define CONFIG_MXC_USB_FLAGS 0
239 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
240 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
243 #define CONFIG_CMD_I2C
244 #define CONFIG_SYS_I2C
245 #define CONFIG_SYS_I2C_MXC
246 #define CONFIG_SYS_I2C_SPEED 100000
247 #define CONFIG_SYS_MXC_I2C3_SPEED 400000
249 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
250 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
251 #define CONFIG_SYS_I2C_EEPROM_BUS 2
254 #define CONFIG_CMD_SATA
255 #define CONFIG_SYS_SATA_MAX_DEVICE 1
256 #define CONFIG_LIBATA
258 #define CONFIG_DWC_AHSATA
259 #define CONFIG_DWC_AHSATA_PORT_ID 0
260 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
263 #define CONFIG_MXC_GPIO
266 #define CONFIG_ZERO_BOOTDELAY_CHECK
267 #define CONFIG_LOADADDR 0x10800000
268 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
269 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
270 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
271 #define CONFIG_SETUP_MEMORY_TAGS
272 #define CONFIG_INITRD_TAG
273 #define CONFIG_REVISION_TAG
274 #define CONFIG_SERIAL_TAG
277 #define CONFIG_SYS_GENERIC_BOARD
278 #define CONFIG_STACKSIZE (128 * 1024)
279 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
280 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
281 #define CONFIG_OF_BOARD_SETUP
284 #include "imx6_spl.h"
285 #define CONFIG_SPL_BOARD_INIT
286 #define CONFIG_SPL_MMC_SUPPORT
287 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 /* offset 64 kb */
288 #define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024)
289 #define CONFIG_SPL_SPI_SUPPORT
290 #define CONFIG_SPL_SPI_FLASH_SUPPORT
291 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
292 #define CONFIG_SPL_SPI_LOAD
294 #endif /* __CONFIG_CM_FX6_H */