3 * Congatec Conga-QEVAl board configuration file.
5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
6 * Based on Freescale i.MX6Q Sabre Lite board configuration file.
7 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
8 * Leo Sartre, <lsartre@adeneo-embedded.com>
10 * SPDX-License-Identifier: GPL-2.0+
13 #ifndef __CONFIG_CGTQMX6EVAL_H
14 #define __CONFIG_CGTQMX6EVAL_H
16 #include "mx6_common.h"
18 #define CONFIG_MACH_TYPE 4122
20 /* Size of malloc() pool */
21 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
23 #define CONFIG_BOARD_EARLY_INIT_F
24 #define CONFIG_MISC_INIT_R
26 #define CONFIG_MXC_UART
27 #define CONFIG_MXC_UART_BASE UART2_BASE
30 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
32 /* Miscellaneous commands */
33 #define CONFIG_CMD_BMODE
36 #define CONFIG_IMX6_THERMAL
38 #define CONFIG_CMD_FUSE
39 #if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
40 #define CONFIG_MXC_OCOTP
44 #define CONFIG_CMD_I2C
45 #define CONFIG_SYS_I2C
46 #define CONFIG_SYS_I2C_MXC
47 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
48 #define CONFIG_SYS_I2C_SPEED 100000
52 #define CONFIG_POWER_I2C
53 #define CONFIG_POWER_PFUZE100
54 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
57 #define CONFIG_CMD_USB
58 #define CONFIG_CMD_FAT
59 #define CONFIG_USB_EHCI
60 #define CONFIG_USB_EHCI_MX6
61 #define CONFIG_USB_STORAGE
62 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
63 #define CONFIG_USB_HOST_ETHER
64 #define CONFIG_USB_ETHER_ASIX
65 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
66 #define CONFIG_MXC_USB_FLAGS 0
67 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
68 #define CONFIG_USB_KEYBOARD
69 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
71 #define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb"
73 #define CONFIG_EXTRA_ENV_SETTINGS \
76 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
79 "fdt_high=0xffffffff\0" \
80 "initrd_high=0xffffffff\0" \
81 "fdt_addr=0x18000000\0" \
85 "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
86 "mmcargs=setenv bootargs console=${console},${baudrate} " \
89 "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
90 "bootscript=echo Running bootscript from mmc ...; " \
92 "loadimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
93 "${boot_dir}/${image}\0" \
94 "loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \
95 "${boot_dir}/${fdt_file}\0" \
96 "mmcboot=echo Booting from mmc ...; " \
98 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
99 "if run loadfdt; then " \
100 "bootz ${loadaddr} - ${fdt_addr}; " \
102 "if test ${boot_fdt} = try; then " \
105 "echo WARN: Cannot load the DT; " \
112 #define CONFIG_BOOTCOMMAND \
113 "mmc dev ${mmcdev};" \
114 "mmc dev ${mmcdev}; if mmc rescan; then " \
115 "if run loadbootscript; then " \
118 "if run loadimage; then " \
121 "echo ERR: Fail to boot from mmc; " \
124 "else echo ERR: Fail to boot from mmc; fi"
126 #define CONFIG_SYS_MEMTEST_START 0x10000000
127 #define CONFIG_SYS_MEMTEST_END 0x10010000
128 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
130 /* Physical Memory Map */
131 #define CONFIG_NR_DRAM_BANKS 1
132 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
133 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
135 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
136 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
137 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
139 #define CONFIG_SYS_INIT_SP_OFFSET \
140 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
141 #define CONFIG_SYS_INIT_SP_ADDR \
142 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
144 /* Environment organization */
145 #define CONFIG_ENV_SIZE (8 * 1024)
147 #define CONFIG_ENV_IS_IN_MMC
149 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
150 #define CONFIG_SYS_MMC_ENV_DEV 0
152 #endif /* __CONFIG_CGTQMX6EVAL_H */