3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * Configuation settings for the CERF250 board.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * High Level Configuration Options
37 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
38 #define CONFIG_CERF250 1 /* on Cerf PXA Board */
39 #define BOARD_LATE_INIT 1
40 #define CONFIG_BAUDRATE 38400
42 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
44 /* we will never enable dcache, because we have to setup MMU first */
45 #define CONFIG_SYS_NO_DCACHE
48 * Size of malloc() pool
50 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
51 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
56 #define CONFIG_DRIVER_SMC91111
57 #define CONFIG_SMC91111_BASE 0x04000300
58 #define CONFIG_SMC_USE_32_BIT
61 * select serial console configuration
63 #define CONFIG_PXA_SERIAL
64 #define CONFIG_FFUART 1 /* we use FFUART on CERF PXA */
66 /* allow to overwrite serial and ethaddr */
67 #define CONFIG_ENV_OVERWRITE
72 #define CONFIG_BOOTP_BOOTFILESIZE
73 #define CONFIG_BOOTP_BOOTPATH
74 #define CONFIG_BOOTP_GATEWAY
75 #define CONFIG_BOOTP_HOSTNAME
79 * Command line configuration.
81 #include <config_cmd_default.h>
84 #define CONFIG_BOOTDELAY 3
85 #define CONFIG_ETHADDR 00:D0:CA:F1:3C:D2
86 #define CONFIG_NETMASK 255.255.255.0
87 #define CONFIG_IPADDR 192.168.0.5
88 #define CONFIG_SERVERIP 192.168.0.2
89 #define CONFIG_BOOTCOMMAND "bootm 0xC0000"
90 #define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400"
91 #define CONFIG_CMDLINE_TAG
93 #if defined(CONFIG_CMD_KGDB)
94 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
95 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
99 * Miscellaneous configurable options
101 #define CONFIG_SYS_HUSH_PARSER 1
102 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
104 #define CONFIG_SYS_LONGHELP /* undef to save memory */
105 #ifdef CONFIG_SYS_HUSH_PARSER
106 #define CONFIG_SYS_PROMPT "uboot$ " /* Monitor Command Prompt */
108 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
110 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
111 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
112 /* Print Buffer Size */
113 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
114 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
115 #define CONFIG_SYS_DEVICE_NULLDEV 1
117 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
118 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
120 #define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
122 #define CONFIG_SYS_HZ 1000
123 #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
125 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
131 * The stack sizes are set up in start.S using the settings below
133 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
134 #ifdef CONFIG_USE_IRQ
135 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
136 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
140 * Physical Memory Map
142 #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
143 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
144 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
145 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
146 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
147 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
148 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
149 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
150 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
152 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
153 #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
154 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
155 #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
156 #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
158 #define CONFIG_SYS_DRAM_BASE 0xa0000000
159 #define CONFIG_SYS_DRAM_SIZE 0x04000000
161 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
168 #define CONFIG_SYS_GPSR0_VAL 0x00408030
169 #define CONFIG_SYS_GPSR1_VAL 0x00BFA882
170 #define CONFIG_SYS_GPSR2_VAL 0x0001C000
171 #define CONFIG_SYS_GPCR0_VAL 0xC0031100
172 #define CONFIG_SYS_GPCR1_VAL 0xFC400300
173 #define CONFIG_SYS_GPCR2_VAL 0x00003FFF
174 #define CONFIG_SYS_GPDR0_VAL 0xC0439330
175 #define CONFIG_SYS_GPDR1_VAL 0xFCFFAB82
176 #define CONFIG_SYS_GPDR2_VAL 0x0001FFFF
177 #define CONFIG_SYS_GAFR0_L_VAL 0x80000000
178 #define CONFIG_SYS_GAFR0_U_VAL 0xA5000010
179 #define CONFIG_SYS_GAFR1_L_VAL 0x60008018
180 #define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA
181 #define CONFIG_SYS_GAFR2_L_VAL 0xAAA0000A
182 #define CONFIG_SYS_GAFR2_U_VAL 0x00000002
184 #define CONFIG_SYS_PSSR_VAL 0x20
189 #define CONFIG_SYS_MSC0_VAL 0x12447FF0
190 #define CONFIG_SYS_MSC1_VAL 0x12BC5554
191 #define CONFIG_SYS_MSC2_VAL 0x7FF97FF1
192 #define CONFIG_SYS_MDCNFG_VAL 0x00001AC9
193 #define CONFIG_SYS_MDREFR_VAL 0x03CDC017
194 #define CONFIG_SYS_MDMRS_VAL 0x00000000
197 * PCMCIA and CF Interfaces
199 #define CONFIG_SYS_MECR_VAL 0x00000000
200 #define CONFIG_SYS_MCMEM0_VAL 0x00010504
201 #define CONFIG_SYS_MCMEM1_VAL 0x00010504
202 #define CONFIG_SYS_MCATT0_VAL 0x00010504
203 #define CONFIG_SYS_MCATT1_VAL 0x00010504
204 #define CONFIG_SYS_MCIO0_VAL 0x00004715
205 #define CONFIG_SYS_MCIO1_VAL 0x00004715
207 #define _LED 0x08000010 /*check this */
208 #define LED_BLANK 0x08000040
209 #define LED_GPIO 0x10
212 * FLASH and environment organization
214 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
215 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
217 /* timeout values are in ticks */
218 #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
219 #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
221 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* 256 KiB */
222 #define CONFIG_ENV_IS_IN_FLASH 1
223 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
224 #define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
227 #endif /* __CONFIG_H */