1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011-2014 OMICRON electronics GmbH
5 * Based on da850evm.h. Original Copyrights follow:
7 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
8 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
17 #define CONFIG_DRIVER_TI_EMAC
18 #define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN
23 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
24 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
25 #define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq()
26 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
27 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
28 #define CONFIG_ARCH_CPU_INIT
29 #define CONFIG_HW_WATCHDOG
30 #define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
31 #define CONFIG_SYS_WDT_PERIOD_LOW \
32 (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
33 #define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
34 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
40 #define CONFIG_SYS_DA850_PLL0_PLLM \
41 ((calimain_get_osc_freq() == 25000000) ? 23 : 24)
42 #define CONFIG_SYS_DA850_PLL1_PLLM \
43 ((calimain_get_osc_freq() == 25000000) ? 20 : 21)
46 * DDR2 memory configuration
48 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
49 DV_DDR_PHY_EXT_STRBEN | \
50 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
52 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
53 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
54 (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
55 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
56 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
57 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
58 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
59 (0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \
60 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
62 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
63 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
65 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
66 (16 << DV_DDR_SDTMR1_RFC_SHIFT) | \
67 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
68 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
69 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
70 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
71 (7 << DV_DDR_SDTMR1_RC_SHIFT) | \
72 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
73 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
75 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
76 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
77 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
78 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
79 (18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
80 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
81 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
82 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
84 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF
85 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
91 #define CONFIG_SYS_DA850_CS2CFG ( \
92 DAVINCI_ABCR_WSETUP(2) | \
93 DAVINCI_ABCR_WSTROBE(5) | \
94 DAVINCI_ABCR_WHOLD(3) | \
95 DAVINCI_ABCR_RSETUP(1) | \
96 DAVINCI_ABCR_RSTROBE(14) | \
97 DAVINCI_ABCR_RHOLD(0) | \
98 DAVINCI_ABCR_TA(3) | \
99 DAVINCI_ABCR_ASIZE_16BIT)
101 /* single 64 MB NOR flash device connected to CS2 and CS3 */
102 #define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG
107 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
108 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
109 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
110 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
112 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
113 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
114 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
115 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
116 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
117 DAVINCI_SYSCFG_SUSPSRC_I2C)
119 /* memtest start addr */
120 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
122 /* memtest will be run on 16MB */
123 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20))
128 #define CONFIG_SYS_NS16550_SERIAL
129 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
130 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
131 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
133 #define CONFIG_FLASH_CFI_DRIVER
134 #define CONFIG_SYS_FLASH_CFI
135 #define CONFIG_SYS_FLASH_PROTECTION
136 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
137 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
138 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
139 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
140 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
141 #define CONFIG_ENV_ADDR \
142 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
143 #define CONFIG_ENV_SIZE (128 << 10)
144 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
145 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
146 #define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */
147 #define CONFIG_SYS_MAX_FLASH_SECT \
148 ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)
151 * Network & Ethernet Configuration
153 #ifdef CONFIG_DRIVER_TI_EMAC
155 #define CONFIG_BOOTP_DNS2
156 #define CONFIG_BOOTP_SEND_HOSTNAME
157 #define CONFIG_NET_RETRY_COUNT 10
161 * U-Boot general configuration
163 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
164 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
165 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
166 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
167 #define CONFIG_LOADADDR 0xc0700000
168 #define CONFIG_MX_CYCLIC
173 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
174 #define CONFIG_CMDLINE_TAG
175 #define CONFIG_REVISION_TAG
176 #define CONFIG_SETUP_MEMORY_TAGS
177 #define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;"
178 #define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */
179 #define CONFIG_RESET_TO_RETRY
182 * Default environment settings
183 * gpio0 = button, gpio1 = led green, gpio2 = led red
184 * verify = n ... disable kernel checksum verification for faster booting
186 #define CONFIG_EXTRA_ENV_SETTINGS \
187 "tftpdir=calimero\0" \
188 "flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \
189 "erase 0x60800000 +0x400000; " \
190 "cp.b $loadaddr 0x60800000 $filesize\0" \
192 "tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \
193 "erase 0x60c00000 +0x2e00000; " \
194 "cp.b $loadaddr 0x60c00000 $filesize\0" \
195 "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \
196 "protect off all; " \
197 "erase 0x60000000 +0x80000; " \
198 "cp.b $loadaddr 0x60000000 $filesize\0" \
199 "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \
200 "erase 0x60080000 +0x780000; " \
201 "cp.b $loadaddr 0x60080000 $filesize\0" \
202 "erase_persistent=erase 0x63a00000 +0x600000;\0" \
203 "bootnor=setenv bootargs console=ttyS2,115200n8 " \
204 "root=/dev/mtdblock3 rw rootfstype=jffs2 " \
205 "rootwait ethaddr=$ethaddr; " \
206 "gpio c 1; gpio s 2; bootm 0x60800000\0" \
207 "bootrlk=gpio s 1; gpio s 2;" \
208 "setenv bootargs console=ttyS2,115200n8 " \
209 "ethaddr=$ethaddr; bootm 0x60080000\0" \
210 "boottftp=setenv bootargs console=ttyS2,115200n8 " \
211 "root=/dev/mtdblock3 rw rootfstype=jffs2 " \
212 "rootwait ethaddr=$ethaddr; " \
213 "tftpboot $loadaddr $tftpdir/uImage;" \
214 "gpio c 1; gpio s 2; bootm $loadaddr\0" \
215 "checkupdate=if test -n $update_flag; then " \
216 "echo Previous update failed - starting RLK; " \
217 "run bootrlk; fi; " \
218 "if test -n $initial_setup; then " \
219 "echo Running initial setup procedure; " \
220 "sleep 1; run flashall; fi\0" \
221 "product=accessory\0" \
224 "if gpio i 0; then run bootnor; fi;\0" \
226 "if gpio i 0; then run bootrlk; fi;\0" \
228 "run checknor; sleep 1;" \
229 "run checknor; sleep 1;" \
230 "run checknor; sleep 1;" \
231 "run checknor; sleep 1;" \
233 "gpio s 1; gpio s 2;" \
234 "echo ---- Release button to boot RLK ----;" \
235 "run checkrlk; sleep 1;" \
236 "run checkrlk; sleep 1;" \
237 "run checkrlk; sleep 1;" \
238 "run checkrlk; sleep 1;" \
239 "run checkrlk; sleep 1;" \
241 "echo ---- Factory reset requested ----;" \
243 "setenv factory_reset true;" \
246 "flashall=run flashrlk;" \
249 "setenv erase_datafs true;" \
250 "setenv initial_setup;" \
254 "clearenv=protect off all;" \
255 "erase 0x60040000 +0x40000;\0" \
257 "altbootcmd=run bootrlk\0"
259 #define CONFIG_PREBOOT \
260 "echo Version: $ver; " \
261 "echo Serial: $serial; " \
262 "echo MAC: $ethaddr; " \
263 "echo Product: $product; " \
264 "gpio c 1; gpio c 2;"
266 /* additions for new relocation code, must added to all boards */
267 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
268 /* initial stack pointer in internal SRAM */
269 #define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
271 #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
274 int calimain_get_osc_freq(void);
277 #include <asm/arch/hardware.h>
279 #endif /* __CONFIG_H */