sunxi: Add support for using MII phy-s with the GMAC nic
[oweals/u-boot.git] / include / configs / calimain.h
1 /*
2  * Copyright (C) 2011-2014 OMICRON electronics GmbH
3  *
4  * Based on da850evm.h. Original Copyrights follow:
5  *
6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8  *
9  * SPDX-License-Identifier:     GPL-2.0+
10  */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 /*
16  * Board
17  */
18 #define CONFIG_DRIVER_TI_EMAC
19 #define MACH_TYPE_CALIMAIN      3528
20 #define CONFIG_MACH_TYPE        MACH_TYPE_CALIMAIN
21 #define CONFIG_SYS_GENERIC_BOARD
22
23 /*
24  * SoC Configuration
25  */
26 #define CONFIG_MACH_DAVINCI_CALIMAIN
27 #define CONFIG_ARM926EJS                /* arm926ejs CPU core */
28 #define CONFIG_SOC_DA8XX                /* TI DA8xx SoC */
29 #define CONFIG_SOC_DA850                /* TI DA850 SoC */
30 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
31 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
32 #define CONFIG_SYS_OSCIN_FREQ           calimain_get_osc_freq()
33 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
34 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
35 #define CONFIG_SYS_TEXT_BASE            0x60000000
36 #define CONFIG_DA850_LOWLEVEL
37 #define CONFIG_SYS_DA850_PLL_INIT
38 #define CONFIG_SYS_DA850_DDR_INIT
39 #define CONFIG_ARCH_CPU_INIT
40 #define CONFIG_DA8XX_GPIO
41 #define CONFIG_HW_WATCHDOG
42 #define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
43 #define CONFIG_SYS_WDT_PERIOD_LOW \
44         (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
45 #define CONFIG_SYS_WDT_PERIOD_HIGH      0x0
46 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
47
48 /*
49  * PLL configuration
50  */
51 #define CONFIG_SYS_DV_CLKMODE          0
52 #define CONFIG_SYS_DA850_PLL0_POSTDIV  1
53 #define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
54 #define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
55 #define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
56 #define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
57 #define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
58 #define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
59 #define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
60
61 #define CONFIG_SYS_DA850_PLL1_POSTDIV  1
62 #define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
63 #define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
64 #define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
65
66 #define CONFIG_SYS_DA850_PLL0_PLLM \
67         ((calimain_get_osc_freq() == 25000000) ? 23 : 24)
68 #define CONFIG_SYS_DA850_PLL1_PLLM \
69         ((calimain_get_osc_freq() == 25000000) ? 20 : 21)
70
71 /*
72  * DDR2 memory configuration
73  */
74 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
75                                         DV_DDR_PHY_EXT_STRBEN | \
76                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
77
78 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
79         (1 << DV_DDR_SDCR_DDR2EN_SHIFT) |       \
80         (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) |    \
81         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
82         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
83         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
84         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
85         (0x3 << DV_DDR_SDCR_IBANK_SHIFT) |      \
86         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
87
88 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
89 #define CONFIG_SYS_DA850_DDR2_SDBCR2    0
90
91 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
92         (16 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
93         (1 << DV_DDR_SDTMR1_RP_SHIFT) |         \
94         (1 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
95         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
96         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
97         (7 << DV_DDR_SDTMR1_RC_SHIFT) |         \
98         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
99         (1 << DV_DDR_SDTMR1_WTR_SHIFT))
100
101 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
102         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
103         (2 << DV_DDR_SDTMR2_XP_SHIFT) |         \
104         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
105         (18 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
106         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
107         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
108         (2 << DV_DDR_SDTMR2_CKE_SHIFT))
109
110 #define CONFIG_SYS_DA850_DDR2_SDRCR     0x000003FF
111 #define CONFIG_SYS_DA850_DDR2_PBBPR     0x30
112
113 /*
114  * Flash memory timing
115  */
116
117 #define CONFIG_SYS_DA850_CS2CFG (       \
118         DAVINCI_ABCR_WSETUP(2) |        \
119         DAVINCI_ABCR_WSTROBE(5) |       \
120         DAVINCI_ABCR_WHOLD(3) |         \
121         DAVINCI_ABCR_RSETUP(1) |        \
122         DAVINCI_ABCR_RSTROBE(14) |      \
123         DAVINCI_ABCR_RHOLD(0) |         \
124         DAVINCI_ABCR_TA(3) |            \
125         DAVINCI_ABCR_ASIZE_16BIT)
126
127 /* single 64 MB NOR flash device connected to CS2 and CS3 */
128 #define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG
129
130 /*
131  * Memory Info
132  */
133 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
134 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
135 #define PHYS_SDRAM_1_SIZE       (128 << 20) /* SDRAM size 128MB */
136 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
137
138 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
139         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
140         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
141         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
142         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
143         DAVINCI_SYSCFG_SUSPSRC_I2C)
144
145 /* memtest start addr */
146 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
147
148 /* memtest will be run on 16MB */
149 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + (16 << 20))
150
151 #define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
152
153 /*
154  * Serial Driver info
155  */
156 #define CONFIG_SYS_NS16550
157 #define CONFIG_SYS_NS16550_SERIAL
158 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
159 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
160 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
161 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
162 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
163
164 #define CONFIG_ENV_IS_IN_FLASH
165 #define CONFIG_FLASH_CFI_DRIVER
166 #define CONFIG_SYS_FLASH_CFI
167 #define CONFIG_SYS_FLASH_PROTECTION
168 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
169 #define CONFIG_SYS_MAX_FLASH_BANKS  1 /* max number of flash banks */
170 #define CONFIG_SYS_FLASH_SECT_SZ    (128 << 10) /* 128KB */
171 #define CONFIG_SYS_FLASH_BASE       DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
172 #define CONFIG_ENV_SECT_SIZE        CONFIG_SYS_FLASH_SECT_SZ
173 #define CONFIG_ENV_ADDR \
174         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
175 #define CONFIG_ENV_SIZE             (128 << 10)
176 #define CONFIG_ENV_ADDR_REDUND      (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
177 #define CONFIG_ENV_SIZE_REDUND      CONFIG_ENV_SIZE
178 #define PHYS_FLASH_SIZE             (64 << 20) /* Flash size 64MB */
179 #define CONFIG_SYS_MAX_FLASH_SECT \
180         ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)
181
182 /*
183  * Network & Ethernet Configuration
184  */
185 #ifdef CONFIG_DRIVER_TI_EMAC
186 #define CONFIG_EMAC_MDIO_PHY_NUM        1
187 #define CONFIG_MII
188 #define CONFIG_BOOTP_DNS
189 #define CONFIG_BOOTP_DNS2
190 #define CONFIG_BOOTP_SEND_HOSTNAME
191 #define CONFIG_NET_RETRY_COUNT  10
192 #endif
193
194 /*
195  * U-Boot general configuration
196  */
197 #define CONFIG_BOOTFILE        "uImage" /* Boot file name */
198 #define CONFIG_SYS_PROMPT      "Calimain > " /* Command Prompt */
199 #define CONFIG_SYS_CBSIZE      1024 /* Console I/O Buffer Size  */
200 #define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
201 #define CONFIG_SYS_MAXARGS     16 /* max number of command args */
202 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
203 #define CONFIG_SYS_LOAD_ADDR   (PHYS_SDRAM_1 + 0x700000)
204 #define CONFIG_LOADADDR        0xc0700000
205 #define CONFIG_VERSION_VARIABLE
206 #define CONFIG_AUTO_COMPLETE
207 #define CONFIG_SYS_HUSH_PARSER
208 #define CONFIG_CMDLINE_EDITING
209 #define CONFIG_SYS_LONGHELP
210 #define CONFIG_CRC32_VERIFY
211 #define CONFIG_MX_CYCLIC
212
213 /*
214  * Linux Information
215  */
216 #define LINUX_BOOT_PARAM_ADDR     (PHYS_SDRAM_1 + 0x100)
217 #define CONFIG_CMDLINE_TAG
218 #define CONFIG_REVISION_TAG
219 #define CONFIG_SETUP_MEMORY_TAGS
220 #define CONFIG_BOOTARGS           ""
221 #define CONFIG_BOOTCOMMAND        "run checkupdate; run checkbutton;"
222 #define CONFIG_BOOTDELAY          0
223 #define CONFIG_ZERO_BOOTDELAY_CHECK   /* check for keypress on bootdelay==0 */
224 #define CONFIG_BOOT_RETRY_TIME    60  /* continue boot after 60 s inactivity */
225 #define CONFIG_AUTOBOOT_KEYED
226 #define CONFIG_AUTOBOOT_DELAY_STR "\x0d" /* press ENTER to interrupt BOOT */
227 #define CONFIG_RESET_TO_RETRY
228
229 /*
230  * Default environment settings
231  * gpio0 = button, gpio1 = led green, gpio2 = led red
232  * verify = n ... disable kernel checksum verification for faster booting
233  */
234 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
235         "tftpdir=calimero\0"                                            \
236         "flashkernel=tftpboot $loadaddr $tftpdir/uImage; "              \
237                 "erase 0x60800000 +0x400000; "                          \
238                 "cp.b $loadaddr 0x60800000 $filesize\0"                 \
239         "flashrootfs="                                                  \
240                 "tftpboot $loadaddr $tftpdir/rootfs.jffs2; "            \
241                 "erase 0x60c00000 +0x2e00000; "                         \
242                 "cp.b $loadaddr 0x60c00000 $filesize\0"                 \
243         "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; "           \
244                 "protect off all; "                                     \
245                 "erase 0x60000000 +0x80000; "                           \
246                 "cp.b $loadaddr 0x60000000 $filesize\0"                 \
247         "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; "             \
248                 "erase 0x60080000 +0x780000; "                          \
249                 "cp.b $loadaddr 0x60080000 $filesize\0"                 \
250         "erase_persistent=erase 0x63a00000 +0x600000;\0"                \
251         "bootnor=setenv bootargs console=ttyS2,115200n8 "               \
252                 "root=/dev/mtdblock3 rw rootfstype=jffs2 "              \
253                 "rootwait ethaddr=$ethaddr; "                           \
254                 "gpio c 1; gpio s 2; bootm 0x60800000\0"                \
255         "bootrlk=gpio s 1; gpio s 2;"                                   \
256                 "setenv bootargs console=ttyS2,115200n8 "               \
257                 "ethaddr=$ethaddr; bootm 0x60080000\0"                  \
258         "boottftp=setenv bootargs console=ttyS2,115200n8 "              \
259                 "root=/dev/mtdblock3 rw rootfstype=jffs2 "              \
260                 "rootwait ethaddr=$ethaddr; "                           \
261                 "tftpboot $loadaddr $tftpdir/uImage;"                   \
262                 "gpio c 1; gpio s 2; bootm $loadaddr\0"                 \
263         "checkupdate=if test -n $update_flag; then "                    \
264                 "echo Previous update failed - starting RLK; "          \
265                 "run bootrlk; fi; "                                     \
266                 "if test -n $initial_setup; then "                      \
267                 "echo Running initial setup procedure; "                \
268                 "sleep 1; run flashall; fi\0"                           \
269         "product=accessory\0"                                           \
270         "serial=XX12345\0"                                              \
271         "checknor="                                                     \
272                 "if gpio i 0; then run bootnor; fi;\0"                  \
273         "checkrlk="                                                     \
274                 "if gpio i 0; then run bootrlk; fi;\0"                  \
275         "checkbutton="                                                  \
276                 "run checknor; sleep 1;"                                \
277                 "run checknor; sleep 1;"                                \
278                 "run checknor; sleep 1;"                                \
279                 "run checknor; sleep 1;"                                \
280                 "run checknor;"                                         \
281                 "gpio s 1; gpio s 2;"                                   \
282                 "echo ---- Release button to boot RLK ----;"            \
283                 "run checkrlk; sleep 1;"                                \
284                 "run checkrlk; sleep 1;"                                \
285                 "run checkrlk; sleep 1;"                                \
286                 "run checkrlk; sleep 1;"                                \
287                 "run checkrlk; sleep 1;"                                \
288                 "run checkrlk;"                                         \
289                 "echo ---- Factory reset requested ----;"               \
290                 "gpio c 1;"                                             \
291                 "setenv factory_reset true;"                            \
292                 "saveenv;"                                              \
293                 "run bootnor;\0"                                        \
294         "flashall=run flashrlk;"                                        \
295                 "run flashkernel;"                                      \
296                 "run flashrootfs;"                                      \
297                 "setenv erase_datafs true;"                             \
298                 "setenv initial_setup;"                                 \
299                 "saveenv;"                                              \
300                 "run bootnor;\0"                                        \
301         "verify=n\0"                                                    \
302         "clearenv=protect off all;"                                     \
303                 "erase 0x60040000 +0x40000;\0"                          \
304         "bootlimit=3\0"                                                 \
305         "altbootcmd=run bootrlk\0"
306
307 #define CONFIG_PREBOOT                  \
308         "echo Version: $ver; "          \
309         "echo Serial: $serial; "        \
310         "echo MAC: $ethaddr; "          \
311         "echo Product: $product; "      \
312         "gpio c 1; gpio c 2;"
313
314 /*
315  * U-Boot commands
316  */
317 #include <config_cmd_default.h>
318 #define CONFIG_CMD_ENV
319 #define CONFIG_CMD_ASKENV
320 #define CONFIG_CMD_DHCP
321 #define CONFIG_CMD_DIAG
322 #define CONFIG_CMD_MII
323 #define CONFIG_CMD_PING
324 #define CONFIG_CMD_SAVES
325 #define CONFIG_CMD_MEMORY
326 #define CONFIG_CMD_GPIO
327
328 #ifndef CONFIG_DRIVER_TI_EMAC
329 #undef CONFIG_CMD_NET
330 #undef CONFIG_CMD_DHCP
331 #undef CONFIG_CMD_MII
332 #undef CONFIG_CMD_PING
333 #endif
334
335 /* additions for new relocation code, must added to all boards */
336 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
337 /* initial stack pointer in internal SRAM */
338 #define CONFIG_SYS_INIT_SP_ADDR         (0x8001ff00)
339
340 #define CONFIG_BOOTCOUNT_LIMIT
341 #define CONFIG_SYS_BOOTCOUNT_LE         /* Use little-endian accessors */
342 #define CONFIG_SYS_BOOTCOUNT_ADDR       DAVINCI_RTC_BASE
343
344 #ifndef __ASSEMBLY__
345 int calimain_get_osc_freq(void);
346 #endif
347
348 #endif /* __CONFIG_H */