1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * esd vme8349 U-Boot configuration file
4 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
6 * (C) Copyright 2006-2010
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * reinhard.arlt@esd-electronics.de
10 * Based on the MPC8349EMDS config.
14 * vme8349 board configuration file.
21 * High Level Configuration Options
23 #define CONFIG_E300 1 /* E300 Family */
25 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
26 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
28 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
29 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
30 #define CONFIG_SYS_MEMTEST_END 0x00100000
35 #define CONFIG_DDR_ECC /* only for ECC DDR module */
36 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
37 #define CONFIG_SPD_EEPROM
38 #define SPD_EEPROM_ADDRESS 0x54
39 #define CONFIG_SYS_READ_SPD vme8349_read_spd
40 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
43 * 32-bit data path mode.
45 * Please note that using this mode for devices with the real density of 64-bit
46 * effectively reduces the amount of available memory due to the effect of
47 * wrapping around while translating address to row/columns, for example in the
48 * 256MB module the upper 128MB get aliased with contents of the lower
49 * 128MB); normally this define should be used for devices with real 32-bit
52 #undef CONFIG_DDR_32BIT
54 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/
55 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
56 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
57 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
58 #define CONFIG_DDR_2T_TIMING
59 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
65 * FLASH on the Local Bus
67 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
68 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
71 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000
74 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
75 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
77 #undef CONFIG_SYS_FLASH_CHECKSUM
78 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
79 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
81 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
83 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
84 #define CONFIG_SYS_RAMBOOT
86 #undef CONFIG_SYS_RAMBOOT
89 #define CONFIG_SYS_INIT_RAM_LOCK 1
90 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
91 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
93 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
94 GENERATED_GBL_DATA_SIZE)
95 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
97 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
98 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
101 * Local Bus LCRR and LBCR regs
102 * LCRR: no DLL bypass, Clock divider is 4
103 * External Local Bus rate is
104 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
106 #define CONFIG_SYS_LBC_LBCR 0x00000000
108 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
113 #define CONFIG_SYS_NS16550_SERIAL
114 #define CONFIG_SYS_NS16550_REG_SIZE 1
115 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
117 #define CONFIG_SYS_BAUDRATE_TABLE \
118 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
120 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
121 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
124 #define CONFIG_SYS_I2C
125 #define CONFIG_SYS_I2C_FSL
126 #define CONFIG_SYS_FSL_I2C_SPEED 400000
127 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
128 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
129 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
130 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
131 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
132 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
133 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
135 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
138 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
139 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
140 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
141 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
145 * Addresses are mapped 1-1.
147 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
148 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
149 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
150 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
151 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
152 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
153 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
154 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
155 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
157 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
158 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
159 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
160 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
161 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
162 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
163 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
164 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
165 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
167 #if defined(CONFIG_PCI)
169 #undef CONFIG_EEPRO100
172 #if !defined(CONFIG_PCI_PNP)
173 #define PCI_ENET0_IOADDR 0xFIXME
174 #define PCI_ENET0_MEMADDR 0xFIXME
175 #define PCI_IDSEL_NUMBER 0xFIXME
178 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
179 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
181 #endif /* CONFIG_PCI */
187 #if defined(CONFIG_TSEC_ENET)
189 #define CONFIG_GMII /* MII PHY management */
191 #define CONFIG_TSEC1_NAME "TSEC0"
193 #define CONFIG_TSEC2_NAME "TSEC1"
194 #define CONFIG_PHY_M88E1111
195 #define TSEC1_PHY_ADDR 0x08
196 #define TSEC2_PHY_ADDR 0x10
197 #define TSEC1_PHYIDX 0
198 #define TSEC2_PHYIDX 0
199 #define TSEC1_FLAGS TSEC_GIGABIT
200 #define TSEC2_FLAGS TSEC_GIGABIT
202 /* Options are: TSEC[0-1] */
203 #define CONFIG_ETHPRIME "TSEC0"
205 #endif /* CONFIG_TSEC_ENET */
210 #ifndef CONFIG_SYS_RAMBOOT
211 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
212 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
213 #define CONFIG_ENV_SIZE 0x2000
215 /* Address and size of Redundant Environment Sector */
216 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
217 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
220 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
221 #define CONFIG_ENV_SIZE 0x2000
224 #define CONFIG_LOADS_ECHO /* echo on for serial download */
225 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
230 #define CONFIG_BOOTP_BOOTFILESIZE
233 * Command line configuration.
235 #define CONFIG_SYS_RTC_BUS_NUM 0x01
236 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
237 #define CONFIG_RTC_RX8025
239 /* Pass Ethernet MAC to VxWorks */
240 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
242 #undef CONFIG_WATCHDOG /* watchdog disabled */
245 * Miscellaneous configurable options
247 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
250 * For booting Linux, the board info and command line data
251 * have to be in the first 256 MB of memory, since this is
252 * the maximum mapped by the Linux kernel during initialization.
254 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
256 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
258 /* System IO Config */
259 #define CONFIG_SYS_SICRH 0
260 #define CONFIG_SYS_SICRL SICRL_LDP_A
262 #define CONFIG_SYS_GPIO1_PRELIM
263 #define CONFIG_SYS_GPIO1_DIR 0x00100000
264 #define CONFIG_SYS_GPIO1_DAT 0x00100000
266 #define CONFIG_SYS_GPIO2_PRELIM
267 #define CONFIG_SYS_GPIO2_DIR 0x78900000
268 #define CONFIG_SYS_GPIO2_DAT 0x70100000
271 #define CONFIG_PCI_INDIRECT_BRIDGE
274 #if defined(CONFIG_CMD_KGDB)
275 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
279 * Environment Configuration
281 #define CONFIG_ENV_OVERWRITE
283 #if defined(CONFIG_TSEC_ENET)
284 #define CONFIG_HAS_ETH0
285 #define CONFIG_HAS_ETH1
288 #define CONFIG_HOSTNAME "VME8349"
289 #define CONFIG_ROOTPATH "/tftpboot/rootfs"
290 #define CONFIG_BOOTFILE "uImage"
292 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
294 #define CONFIG_EXTRA_ENV_SETTINGS \
296 "hostname=vme8349\0" \
297 "nfsargs=setenv bootargs root=/dev/nfs rw " \
298 "nfsroot=${serverip}:${rootpath}\0" \
299 "ramargs=setenv bootargs root=/dev/ram rw\0" \
300 "addip=setenv bootargs ${bootargs} " \
301 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
302 ":${hostname}:${netdev}:off panic=1\0" \
303 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
304 "flash_nfs=run nfsargs addip addtty;" \
305 "bootm ${kernel_addr}\0" \
306 "flash_self=run ramargs addip addtty;" \
307 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
308 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
310 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
311 "update=protect off fff00000 fff3ffff; " \
312 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
313 "upd=run load update\0" \
315 "fdtfile=vme8349.dtb\0" \
318 #define CONFIG_NFSBOOTCOMMAND \
319 "setenv bootargs root=/dev/nfs rw " \
320 "nfsroot=$serverip:$rootpath " \
321 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
323 "console=$consoledev,$baudrate $othbootargs;" \
324 "tftp $loadaddr $bootfile;" \
325 "tftp $fdtaddr $fdtfile;" \
326 "bootm $loadaddr - $fdtaddr"
328 #define CONFIG_RAMBOOTCOMMAND \
329 "setenv bootargs root=/dev/ram rw " \
330 "console=$consoledev,$baudrate $othbootargs;" \
331 "tftp $ramdiskaddr $ramdiskfile;" \
332 "tftp $loadaddr $bootfile;" \
333 "tftp $fdtaddr $fdtfile;" \
334 "bootm $loadaddr $ramdiskaddr $fdtaddr"
336 #define CONFIG_BOOTCOMMAND "run flash_self"
339 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
340 unsigned char *buffer, int len);
343 #endif /* __CONFIG_H */