1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * esd vme8349 U-Boot configuration file
4 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
6 * (C) Copyright 2006-2010
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * reinhard.arlt@esd-electronics.de
10 * Based on the MPC8349EMDS config.
14 * vme8349 board configuration file.
21 * High Level Configuration Options
23 #define CONFIG_E300 1 /* E300 Family */
25 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
26 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
28 #define CONFIG_PCI_66M
30 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
32 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
35 #ifndef CONFIG_SYS_CLK_FREQ
37 #define CONFIG_SYS_CLK_FREQ 66000000
38 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
40 #define CONFIG_SYS_CLK_FREQ 33000000
41 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
45 #define CONFIG_SYS_IMMR 0xE0000000
47 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
48 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
49 #define CONFIG_SYS_MEMTEST_END 0x00100000
54 #define CONFIG_DDR_ECC /* only for ECC DDR module */
55 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
56 #define CONFIG_SPD_EEPROM
57 #define SPD_EEPROM_ADDRESS 0x54
58 #define CONFIG_SYS_READ_SPD vme8349_read_spd
59 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
62 * 32-bit data path mode.
64 * Please note that using this mode for devices with the real density of 64-bit
65 * effectively reduces the amount of available memory due to the effect of
66 * wrapping around while translating address to row/columns, for example in the
67 * 256MB module the upper 128MB get aliased with contents of the lower
68 * 128MB); normally this define should be used for devices with real 32-bit
71 #undef CONFIG_DDR_32BIT
73 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
75 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
76 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
77 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
78 #define CONFIG_DDR_2T_TIMING
79 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
85 * FLASH on the Local Bus
87 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
88 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
89 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
90 BR_PS_16 | /* 16bit */ \
91 BR_MS_GPCM | /* MSEL = GPCM */ \
94 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
104 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
105 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
107 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000
108 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
113 #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
116 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
117 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
119 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
120 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
122 #undef CONFIG_SYS_FLASH_CHECKSUM
123 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
124 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
126 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
128 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
129 #define CONFIG_SYS_RAMBOOT
131 #undef CONFIG_SYS_RAMBOOT
134 #define CONFIG_SYS_INIT_RAM_LOCK 1
135 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
136 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
138 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
139 GENERATED_GBL_DATA_SIZE)
140 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
142 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
143 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
146 * Local Bus LCRR and LBCR regs
147 * LCRR: no DLL bypass, Clock divider is 4
148 * External Local Bus rate is
149 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
151 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
152 #define CONFIG_SYS_LBC_LBCR 0x00000000
154 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
159 #define CONFIG_SYS_NS16550_SERIAL
160 #define CONFIG_SYS_NS16550_REG_SIZE 1
161 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
163 #define CONFIG_SYS_BAUDRATE_TABLE \
164 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
166 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
167 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
170 #define CONFIG_SYS_I2C
171 #define CONFIG_SYS_I2C_FSL
172 #define CONFIG_SYS_FSL_I2C_SPEED 400000
173 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
174 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
175 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
176 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
177 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
178 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
179 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
181 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
184 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
185 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
186 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
187 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
191 * Addresses are mapped 1-1.
193 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
194 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
195 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
196 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
197 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
198 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
199 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
200 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
201 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
203 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
204 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
205 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
206 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
207 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
208 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
209 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
210 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
211 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
213 #if defined(CONFIG_PCI)
215 #undef CONFIG_EEPRO100
218 #if !defined(CONFIG_PCI_PNP)
219 #define PCI_ENET0_IOADDR 0xFIXME
220 #define PCI_ENET0_MEMADDR 0xFIXME
221 #define PCI_IDSEL_NUMBER 0xFIXME
224 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
225 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
227 #endif /* CONFIG_PCI */
233 #if defined(CONFIG_TSEC_ENET)
235 #define CONFIG_GMII /* MII PHY management */
237 #define CONFIG_TSEC1_NAME "TSEC0"
239 #define CONFIG_TSEC2_NAME "TSEC1"
240 #define CONFIG_PHY_M88E1111
241 #define TSEC1_PHY_ADDR 0x08
242 #define TSEC2_PHY_ADDR 0x10
243 #define TSEC1_PHYIDX 0
244 #define TSEC2_PHYIDX 0
245 #define TSEC1_FLAGS TSEC_GIGABIT
246 #define TSEC2_FLAGS TSEC_GIGABIT
248 /* Options are: TSEC[0-1] */
249 #define CONFIG_ETHPRIME "TSEC0"
251 #endif /* CONFIG_TSEC_ENET */
256 #ifndef CONFIG_SYS_RAMBOOT
257 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
258 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
259 #define CONFIG_ENV_SIZE 0x2000
261 /* Address and size of Redundant Environment Sector */
262 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
263 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
266 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
267 #define CONFIG_ENV_SIZE 0x2000
270 #define CONFIG_LOADS_ECHO /* echo on for serial download */
271 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
276 #define CONFIG_BOOTP_BOOTFILESIZE
279 * Command line configuration.
281 #define CONFIG_SYS_RTC_BUS_NUM 0x01
282 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
283 #define CONFIG_RTC_RX8025
285 /* Pass Ethernet MAC to VxWorks */
286 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
288 #undef CONFIG_WATCHDOG /* watchdog disabled */
291 * Miscellaneous configurable options
293 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
296 * For booting Linux, the board info and command line data
297 * have to be in the first 256 MB of memory, since this is
298 * the maximum mapped by the Linux kernel during initialization.
300 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
302 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
304 #define CONFIG_SYS_HRCW_LOW (\
305 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
306 HRCWL_DDR_TO_SCB_CLK_1X1 |\
307 HRCWL_CSB_TO_CLKIN |\
309 HRCWL_CORE_TO_CSB_2X1)
311 #if defined(PCI_64BIT)
312 #define CONFIG_SYS_HRCW_HIGH (\
315 HRCWH_PCI1_ARBITER_ENABLE |\
316 HRCWH_PCI2_ARBITER_DISABLE |\
318 HRCWH_FROM_0X00000100 |\
319 HRCWH_BOOTSEQ_DISABLE |\
320 HRCWH_SW_WATCHDOG_DISABLE |\
321 HRCWH_ROM_LOC_LOCAL_16BIT |\
322 HRCWH_TSEC1M_IN_GMII |\
323 HRCWH_TSEC2M_IN_GMII)
325 #define CONFIG_SYS_HRCW_HIGH (\
328 HRCWH_PCI1_ARBITER_ENABLE |\
329 HRCWH_PCI2_ARBITER_ENABLE |\
331 HRCWH_FROM_0X00000100 |\
332 HRCWH_BOOTSEQ_DISABLE |\
333 HRCWH_SW_WATCHDOG_DISABLE |\
334 HRCWH_ROM_LOC_LOCAL_16BIT |\
335 HRCWH_TSEC1M_IN_GMII |\
336 HRCWH_TSEC2M_IN_GMII)
339 /* System IO Config */
340 #define CONFIG_SYS_SICRH 0
341 #define CONFIG_SYS_SICRL SICRL_LDP_A
343 #define CONFIG_SYS_HID0_INIT 0x000000000
344 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
345 HID0_ENABLE_INSTRUCTION_CACHE)
347 #define CONFIG_SYS_HID2 HID2_HBE
349 #define CONFIG_SYS_GPIO1_PRELIM
350 #define CONFIG_SYS_GPIO1_DIR 0x00100000
351 #define CONFIG_SYS_GPIO1_DAT 0x00100000
353 #define CONFIG_SYS_GPIO2_PRELIM
354 #define CONFIG_SYS_GPIO2_DIR 0x78900000
355 #define CONFIG_SYS_GPIO2_DAT 0x70100000
357 #define CONFIG_HIGH_BATS /* High BATs supported */
359 /* DDR @ 0x00000000 */
360 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
362 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
365 /* PCI @ 0x80000000 */
367 #define CONFIG_PCI_INDIRECT_BRIDGE
368 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
370 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
372 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
373 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
374 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
377 #define CONFIG_SYS_IBAT1L (0)
378 #define CONFIG_SYS_IBAT1U (0)
379 #define CONFIG_SYS_IBAT2L (0)
380 #define CONFIG_SYS_IBAT2U (0)
383 #ifdef CONFIG_MPC83XX_PCI2
384 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
386 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
388 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
389 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
390 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
393 #define CONFIG_SYS_IBAT3L (0)
394 #define CONFIG_SYS_IBAT3U (0)
395 #define CONFIG_SYS_IBAT4L (0)
396 #define CONFIG_SYS_IBAT4U (0)
399 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
400 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
401 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
402 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
405 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
406 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
408 #if (CONFIG_SYS_DDR_SIZE == 512)
409 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
410 BATL_PP_RW | BATL_MEMCOHERENCE)
411 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
412 BATU_BL_256M | BATU_VS | BATU_VP)
414 #define CONFIG_SYS_IBAT7L (0)
415 #define CONFIG_SYS_IBAT7U (0)
418 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
419 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
420 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
421 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
422 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
423 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
424 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
425 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
426 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
427 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
428 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
429 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
430 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
431 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
432 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
433 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
435 #if defined(CONFIG_CMD_KGDB)
436 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
440 * Environment Configuration
442 #define CONFIG_ENV_OVERWRITE
444 #if defined(CONFIG_TSEC_ENET)
445 #define CONFIG_HAS_ETH0
446 #define CONFIG_HAS_ETH1
449 #define CONFIG_HOSTNAME "VME8349"
450 #define CONFIG_ROOTPATH "/tftpboot/rootfs"
451 #define CONFIG_BOOTFILE "uImage"
453 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
455 #define CONFIG_EXTRA_ENV_SETTINGS \
457 "hostname=vme8349\0" \
458 "nfsargs=setenv bootargs root=/dev/nfs rw " \
459 "nfsroot=${serverip}:${rootpath}\0" \
460 "ramargs=setenv bootargs root=/dev/ram rw\0" \
461 "addip=setenv bootargs ${bootargs} " \
462 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
463 ":${hostname}:${netdev}:off panic=1\0" \
464 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
465 "flash_nfs=run nfsargs addip addtty;" \
466 "bootm ${kernel_addr}\0" \
467 "flash_self=run ramargs addip addtty;" \
468 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
469 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
471 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
472 "update=protect off fff00000 fff3ffff; " \
473 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
474 "upd=run load update\0" \
476 "fdtfile=vme8349.dtb\0" \
479 #define CONFIG_NFSBOOTCOMMAND \
480 "setenv bootargs root=/dev/nfs rw " \
481 "nfsroot=$serverip:$rootpath " \
482 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
484 "console=$consoledev,$baudrate $othbootargs;" \
485 "tftp $loadaddr $bootfile;" \
486 "tftp $fdtaddr $fdtfile;" \
487 "bootm $loadaddr - $fdtaddr"
489 #define CONFIG_RAMBOOTCOMMAND \
490 "setenv bootargs root=/dev/ram rw " \
491 "console=$consoledev,$baudrate $othbootargs;" \
492 "tftp $ramdiskaddr $ramdiskfile;" \
493 "tftp $loadaddr $bootfile;" \
494 "tftp $fdtaddr $fdtfile;" \
495 "bootm $loadaddr $ramdiskaddr $fdtaddr"
497 #define CONFIG_BOOTCOMMAND "run flash_self"
500 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
501 unsigned char *buffer, int len);
504 #endif /* __CONFIG_H */