2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
37 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
38 #define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */
40 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
42 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
44 #define CONFIG_NO_SERIAL_EEPROM
45 /*#undef CONFIG_NO_SERIAL_EEPROM*/
46 /*----------------------------------------------------------------------------*/
47 #ifdef CONFIG_NO_SERIAL_EEPROM
50 !-------------------------------------------------------------------------------
51 ! Defines for entry options.
52 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
53 ! are plugged in the board will be utilized as non-ECC DIMMs.
54 !-------------------------------------------------------------------------------
56 #define AUTO_MEMORY_CONFIG
57 #define DIMM_READ_ADDR 0xAB
58 #define DIMM_WRITE_ADDR 0xAA
61 !-------------------------------------------------------------------------------
62 ! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
63 ! assuming a 33MHz input clock to the 405EP from the C9531.
64 !-------------------------------------------------------------------------------
66 #define PLLMR0_DEFAULT PLLMR0_266_133_66
67 #define PLLMR1_DEFAULT PLLMR1_266_133_66
70 /*----------------------------------------------------------------------------*/
73 * Define here the location of the environment variables (FLASH or NVRAM).
74 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
75 * supported for backward compatibility.
78 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
80 #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
83 #define CONFIG_PREBOOT "echo;" \
84 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
87 #undef CONFIG_BOOTARGS
89 #define CONFIG_EXTRA_ENV_SETTINGS \
91 "hostname=bubinga\0" \
92 "nfsargs=setenv bootargs root=/dev/nfs rw " \
93 "nfsroot=${serverip}:${rootpath}\0" \
94 "ramargs=setenv bootargs root=/dev/ram rw\0" \
95 "addip=setenv bootargs ${bootargs} " \
96 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
97 ":${hostname}:${netdev}:off panic=1\0" \
98 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
99 "flash_nfs=run nfsargs addip addtty;" \
100 "bootm ${kernel_addr}\0" \
101 "flash_self=run ramargs addip addtty;" \
102 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
103 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
105 "rootpath=/opt/eldk/ppc_4xx\0" \
106 "bootfile=/tftpboot/bubinga/uImage\0" \
107 "kernel_addr=fff80000\0" \
108 "ramdisk_addr=fff90000\0" \
109 "initrd_high=30000000\0" \
110 "load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \
111 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
112 "cp.b 100000 fffc0000 40000;" \
113 "setenv filesize;saveenv\0" \
114 "upd=run load;run update\0" \
116 #define CONFIG_BOOTCOMMAND "run net_nfs"
119 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
121 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
124 #define CONFIG_BAUDRATE 115200
126 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
127 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
129 #define CONFIG_MII 1 /* MII PHY management */
130 #define CONFIG_PHY_ADDR 1 /* PHY address */
131 #define CONFIG_HAS_ETH1
132 #define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
133 #define CONFIG_NET_MULTI 1
134 #define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
136 #define CONFIG_NETCONSOLE /* include NetConsole support */
138 #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
140 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
157 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
158 #include <cmd_confdefs.h>
160 #undef CONFIG_WATCHDOG /* watchdog disabled */
162 #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
165 * Miscellaneous configurable options
167 #define CFG_LONGHELP /* undef to save memory */
168 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
169 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
170 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
172 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
174 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
175 #define CFG_MAXARGS 16 /* max number of command args */
176 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
178 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
179 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
182 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
183 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
184 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
185 * The Linux BASE_BAUD define should match this configuration.
186 * baseBaud = cpuClock/(uartDivisor*16)
187 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
188 * set Linux BASE_BAUD to 403200.
190 #undef CONFIG_SERIAL_SOFTWARE_FIFO
191 #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
192 #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
193 #define CFG_BASE_BAUD 691200
195 /* The following table includes the supported baudrates */
196 #define CFG_BAUDRATE_TABLE \
197 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
199 #define CFG_LOAD_ADDR 0x100000 /* default load address */
200 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
202 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
204 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
205 #define CONFIG_LOOPW 1 /* enable loopw command */
206 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
207 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
208 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
210 /*-----------------------------------------------------------------------
212 *-----------------------------------------------------------------------
214 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
215 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
216 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
217 #define CFG_I2C_SLAVE 0x7F
219 #define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
220 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
222 #if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
223 #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
224 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
227 /*-----------------------------------------------------------------------
229 *-----------------------------------------------------------------------
231 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
232 #define PCI_HOST_FORCE 1 /* configure as pci host */
233 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
235 #define CONFIG_PCI /* include pci support */
236 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
237 #define CONFIG_PCI_PNP /* do pci plug-and-play */
238 /* resource configuration */
239 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
241 #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
242 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
243 #define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
244 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
245 #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
246 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
247 #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
248 #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
249 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
251 /*-----------------------------------------------------------------------
252 * External peripheral base address
253 *-----------------------------------------------------------------------
255 #define CFG_KEY_REG_BASE_ADDR 0xF0100000
256 #define CFG_IR_REG_BASE_ADDR 0xF0200000
257 #define CFG_FPGA_REG_BASE_ADDR 0xF0300000
259 /*-----------------------------------------------------------------------
260 * Start addresses for the final memory configuration
261 * (Set up by the startup code)
262 * Please note that CFG_SDRAM_BASE _must_ start at 0
264 #define CFG_SDRAM_BASE 0x00000000
265 #define CFG_SRAM_BASE 0xFFF00000
266 #define CFG_FLASH_BASE 0xFFF80000
267 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
268 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
269 #define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
272 * For booting Linux, the board info and command line data
273 * have to be in the first 8 MB of memory, since this is
274 * the maximum mapped by the Linux kernel during initialization.
276 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
278 /*-----------------------------------------------------------------------
281 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
282 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
284 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
285 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
287 #define CFG_FLASH_ADDR0 0x5555
288 #define CFG_FLASH_ADDR1 0x2aaa
289 #define CFG_FLASH_WORD_SIZE unsigned char
291 #ifdef CFG_ENV_IS_IN_FLASH
292 #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
293 #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
294 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
296 /* Address and size of Redundant Environment Sector */
297 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
298 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
299 #endif /* CFG_ENV_IS_IN_FLASH */
301 /*-----------------------------------------------------------------------
304 #define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
305 #define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
307 #ifdef CFG_ENV_IS_IN_NVRAM
308 #define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
309 #define CFG_ENV_ADDR \
310 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
312 /*-----------------------------------------------------------------------
313 * Cache Configuration
315 #define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */
316 #define CFG_CACHELINE_SIZE 32 /* ... */
317 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
318 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
322 * Init Memory Controller:
324 * BR0/1 and OR0/1 (FLASH)
327 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
328 #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
330 /*-----------------------------------------------------------------------
331 * Definitions for initial stack pointer and data area (in data cache)
333 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
334 #define CFG_TEMP_STACK_OCM 1
336 /* On Chip Memory location */
337 #define CFG_OCM_DATA_ADDR 0xF8000000
338 #define CFG_OCM_DATA_SIZE 0x1000
339 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
340 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
342 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
343 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
344 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
346 /*-----------------------------------------------------------------------
347 * External Bus Controller (EBC) Setup
350 /* Memory Bank 0 (Flash/SRAM) initialization */
351 #define CFG_EBC_PB0AP 0x04006000
352 #define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
354 /* Memory Bank 1 (NVRAM/RTC) initialization */
355 #define CFG_EBC_PB1AP 0x04041000
356 #define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
358 /* Memory Bank 2 (not used) initialization */
359 #define CFG_EBC_PB2AP 0x00000000
360 #define CFG_EBC_PB2CR 0x00000000
362 /* Memory Bank 2 (not used) initialization */
363 #define CFG_EBC_PB3AP 0x00000000
364 #define CFG_EBC_PB3CR 0x00000000
366 /* Memory Bank 4 (FPGA regs) initialization */
367 #define CFG_EBC_PB4AP 0x01815000
368 #define CFG_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
370 /*-----------------------------------------------------------------------
371 * Definitions for Serial Presence Detect EEPROM address
372 * (to get SDRAM settings)
374 #define SPD_EEPROM_ADDRESS 0x55
376 /*-----------------------------------------------------------------------
377 * Definitions for GPIO setup (PPC405EP specific)
379 * GPIO0[0] - External Bus Controller BLAST output
380 * GPIO0[1-9] - Instruction trace outputs
381 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
382 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
383 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
384 * GPIO0[24-27] - UART0 control signal inputs/outputs
385 * GPIO0[28-29] - UART1 data signal input/output
386 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
388 #define CFG_GPIO0_OSRH 0x55555555
389 #define CFG_GPIO0_OSRL 0x40000110
390 #define CFG_GPIO0_ISR1H 0x00000000
391 #define CFG_GPIO0_ISR1L 0x15555445
392 #define CFG_GPIO0_TSRH 0x00000000
393 #define CFG_GPIO0_TSRL 0x00000000
394 #define CFG_GPIO0_TCR 0xFFFF8014
396 /*-----------------------------------------------------------------------
397 * Some BUBINGA stuff...
399 #define NVRAM_BASE 0xF0000000
400 #define FPGA_REG0 0xF0300000 /* FPGA Reg 0 */
401 #define FPGA_REG1 0xF0300001 /* FPGA Reg 1 */
402 #define NVRVFY1 0x4f532d4f /* used to determine if state data in */
403 #define NVRVFY2 0x50454e00 /* NVRAM initialized (ascii for OS-OPEN)*/
405 #define FPGA_REG0_F_RANGE 0x80 /* SDRAM PLL freq range */
406 #define FPGA_REG0_EXT_INT_DIS 0x20 /* External interface disable */
407 #define FPGA_REG0_LED_MASK 0x07 /* Board LEDs DS9, DS10, and DS11 */
408 #define FPGA_REG0_LED0 0x04 /* Turn on LED0 */
409 #define FPGA_REG0_LED1 0x02 /* Turn on LED1 */
410 #define FPGA_REG0_LED2 0x01 /* Turn on LED2 */
412 #define FPGA_REG1_SSPEC_DIS 0x80 /* C9531 Spread Spectrum disabled */
413 #define FPGA_REG1_OFFBD_PCICLK 0x40 /* Onboard PCI clock selected */
414 #define FPGA_REG1_CLOCK_MASK 0x30 /* Mask for C9531 output freq select */
415 #define FPGA_REG1_CLOCK_BIT_SHIFT 4
416 #define FPGA_REG1_PCI_INT_ARB 0x08 /* PCI Internal arbiter selected */
417 #define FPGA_REG1_PCI_FREQ 0x04 /* PCI Frequency select */
418 #define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */
419 #define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */
422 * Internal Definitions
426 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
427 #define BOOTFLAG_WARM 0x02 /* Software reboot */
429 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
430 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
431 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
434 #endif /* __CONFIG_H */