2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_BMS2003
37 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
38 #define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
41 #define CONFIG_NEC_NL6448BC33_54 /* NEC NL6448BC33_54 display */
43 #ifdef CONFIG_LCD /* with LCD controller ? */
44 #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
47 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
48 #undef CONFIG_8xx_CONS_SMC2
49 #undef CONFIG_8xx_CONS_NONE
50 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
52 #define CONFIG_BOOTCOUNT_LIMIT
54 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
56 #define CONFIG_BOARD_TYPES 1 /* support board types */
58 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
60 #undef CONFIG_BOOTARGS
62 #define CONFIG_EXTRA_ENV_SETTINGS \
64 "nfsargs=setenv bootargs root=/dev/nfs rw " \
65 "nfsroot=$(serverip):$(rootpath)\0" \
66 "ramargs=setenv bootargs root=/dev/ram rw\0" \
67 "addip=setenv bootargs $(bootargs) " \
68 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
69 ":$(hostname):$(netdev):off panic=1\0" \
70 "flash_nfs=run nfsargs addip;" \
71 "bootm $(kernel_addr)\0" \
72 "flash_self=run ramargs addip;" \
73 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
74 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
75 "rootpath=/opt/eldk/ppc_8xx\0" \
76 "bootfile=/tftpboot/TQM860L/uImage\0" \
77 "kernel_addr=40040000\0" \
78 "ramdisk_addr=40100000\0" \
80 #define CONFIG_BOOTCOMMAND "run flash_self"
82 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
83 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
85 /* enable I2C and select the hardware/software driver */
86 #undef CONFIG_HARD_I2C /* I2C with hardware support */
87 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
89 #define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */
90 #define CFG_I2C_SLAVE 0xFE
92 /* Software (bit-bang) I2C driver configuration */
93 #define PB_SCL 0x00000020 /* PB 26 */
94 #define PB_SDA 0x00000010 /* PB 27 */
96 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
97 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
98 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
99 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
100 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
101 else immr->im_cpm.cp_pbdat &= ~PB_SDA
102 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
103 else immr->im_cpm.cp_pbdat &= ~PB_SCL
104 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
106 #undef CONFIG_WATCHDOG /* watchdog disabled */
108 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
110 #define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
112 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
114 #define CONFIG_MAC_PARTITION
115 #define CONFIG_DOS_PARTITION
117 #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
118 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
120 #ifdef CONFIG_SPLASH_SCREEN
121 # define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
129 # define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
137 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
138 #include <cmd_confdefs.h>
141 * Miscellaneous configurable options
143 #define CFG_LONGHELP /* undef to save memory */
144 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
147 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
149 #ifdef CFG_HUSH_PARSER
150 #define CFG_PROMPT_HUSH_PS2 "> "
153 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
154 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
156 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
158 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
159 #define CFG_MAXARGS 16 /* max number of command args */
160 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
162 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
163 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
165 #define CFG_LOAD_ADDR 0x100000 /* default load address */
167 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
169 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
172 * Low Level Configuration Settings
173 * (address mappings, register initial values, etc.)
174 * You should know what you are doing if you make changes here.
176 /*-----------------------------------------------------------------------
177 * Internal Memory Mapped Register
179 #define CFG_IMMR 0xFFF00000
181 /*-----------------------------------------------------------------------
182 * Definitions for initial stack pointer and data area (in DPRAM)
184 #define CFG_INIT_RAM_ADDR CFG_IMMR
185 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
186 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
187 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
188 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
190 /*-----------------------------------------------------------------------
191 * Start addresses for the final memory configuration
192 * (Set up by the startup code)
193 * Please note that CFG_SDRAM_BASE _must_ start at 0
195 #define CFG_SDRAM_BASE 0x00000000
196 #define CFG_FLASH_BASE 0x40000000
197 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
198 #define CFG_MONITOR_BASE CFG_FLASH_BASE
199 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
202 * For booting Linux, the board info and command line data
203 * have to be in the first 8 MB of memory, since this is
204 * the maximum mapped by the Linux kernel during initialization.
206 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
208 /*-----------------------------------------------------------------------
211 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
212 #define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
214 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
215 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
217 #define CFG_ENV_IS_IN_FLASH 1
218 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
219 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
221 /* Address and size of Redundant Environment Sector */
222 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
223 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
225 /*-----------------------------------------------------------------------
226 * Hardware Information Block
228 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
229 #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
230 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
232 /*-----------------------------------------------------------------------
233 * Cache Configuration
235 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
236 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
237 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
240 /*-----------------------------------------------------------------------
241 * SYPCR - System Protection Control 11-9
242 * SYPCR can only be written once after reset!
243 *-----------------------------------------------------------------------
244 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
246 #if defined(CONFIG_WATCHDOG)
247 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
248 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
250 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
253 /*-----------------------------------------------------------------------
254 * SIUMCR - SIU Module Configuration 11-6
255 *-----------------------------------------------------------------------
256 * PCMCIA config., multi-function pin tri-state
258 #ifndef CONFIG_CAN_DRIVER
259 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
260 #else /* we must activate GPL5 in the SIUMCR for CAN */
261 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
262 #endif /* CONFIG_CAN_DRIVER */
264 /*-----------------------------------------------------------------------
265 * TBSCR - Time Base Status and Control 11-26
266 *-----------------------------------------------------------------------
267 * Clear Reference Interrupt Status, Timebase freezing enabled
269 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
271 /*-----------------------------------------------------------------------
272 * RTCSC - Real-Time Clock Status and Control Register 11-27
273 *-----------------------------------------------------------------------
275 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
277 /*-----------------------------------------------------------------------
278 * PISCR - Periodic Interrupt Status and Control 11-31
279 *-----------------------------------------------------------------------
280 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
282 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
284 /*-----------------------------------------------------------------------
285 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
286 *-----------------------------------------------------------------------
287 * Reset PLL lock status sticky bit, timer expired status bit and timer
288 * interrupt status bit
290 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
292 #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
294 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
295 #else /* up to 66 MHz we use a 1:1 clock */
296 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
297 #endif /* CONFIG_80MHz */
299 /*-----------------------------------------------------------------------
300 * SCCR - System Clock and reset Control Register 15-27
301 *-----------------------------------------------------------------------
302 * Set clock output, timebase and RTC source and divider,
303 * power management and some other internal clocks
305 #define SCCR_MASK SCCR_EBDF11
306 #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
307 #define CFG_SCCR (/* SCCR_TBS | */ \
308 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
309 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
311 #else /* up to 66 MHz we use a 1:1 clock */
312 #define CFG_SCCR (SCCR_TBS | \
313 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
314 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
316 #endif /* CONFIG_80MHz */
318 /*-----------------------------------------------------------------------
320 *-----------------------------------------------------------------------
323 #ifndef CONFIG_BMS2003
324 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
325 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
326 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
327 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
328 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
329 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
330 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
331 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
332 #else /* CONFIG_BMS2003 */
333 #define CFG_PCMCIA_MEM_ADDR (0xE0100000)
334 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
335 #define CFG_PCMCIA_DMA_ADDR (0xE4100000)
336 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
337 #define CFG_PCMCIA_ATTRB_ADDR (0xE8100000)
338 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
339 #define CFG_PCMCIA_IO_ADDR (0xEC100000)
340 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
341 #define NSCU_OE_INV 1 /* PCMCIA_GCRX_CXOE is inverted */
344 /*-----------------------------------------------------------------------
345 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
346 *-----------------------------------------------------------------------
349 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
351 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
352 #undef CONFIG_IDE_LED /* LED for ide not supported */
353 #undef CONFIG_IDE_RESET /* reset for ide not supported */
355 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
356 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
358 #define CFG_ATA_IDE0_OFFSET 0x0000
360 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
362 /* Offset for data I/O */
363 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
365 /* Offset for normal register accesses */
366 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
368 /* Offset for alternate registers */
369 #define CFG_ATA_ALT_OFFSET 0x0100
371 /*-----------------------------------------------------------------------
373 *-----------------------------------------------------------------------
379 * Init Memory Controller:
381 * BR0/1 and OR0/1 (FLASH)
384 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
385 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
387 /* used to re-map FLASH both when starting from SRAM or FLASH:
388 * restrict access enough to keep SRAM working (if any)
389 * but not too much to meddle with FLASH accesses
391 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
392 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
397 #if defined(CONFIG_80MHz)
398 /* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
399 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
400 OR_SCY_3_CLK | OR_EHTR | OR_BI)
401 #elif defined(CONFIG_66MHz)
402 /* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
403 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
404 OR_SCY_3_CLK | OR_EHTR | OR_BI)
406 /* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
407 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
408 OR_SCY_2_CLK | OR_EHTR | OR_BI)
409 #endif /*CONFIG_??MHz */
411 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
412 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
413 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
415 #define CFG_OR1_REMAP CFG_OR0_REMAP
416 #define CFG_OR1_PRELIM CFG_OR0_PRELIM
417 #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
420 * BR2/3 and OR2/3 (SDRAM)
423 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
424 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
425 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
427 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
428 #define CFG_OR_TIMING_SDRAM 0x00000A00
430 #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
431 #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
433 #ifndef CONFIG_CAN_DRIVER
434 #define CFG_OR3_PRELIM CFG_OR2_PRELIM
435 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
436 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
437 #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
438 #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
439 #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
440 #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
441 BR_PS_8 | BR_MS_UPMB | BR_V )
442 #endif /* CONFIG_CAN_DRIVER */
445 * Memory Periodic Timer Prescaler
447 * The Divider for PTA (refresh timer) configuration is based on an
448 * example SDRAM configuration (64 MBit, one bank). The adjustment to
449 * the number of chip selects (NCS) and the actually needed refresh
450 * rate is done by setting MPTPR.
452 * PTA is calculated from
453 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
455 * gclk CPU clock (not bus clock!)
456 * Trefresh Refresh cycle * 4 (four word bursts used)
458 * 4096 Rows from SDRAM example configuration
459 * 1000 factor s -> ms
460 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
461 * 4 Number of refresh cycles per period
462 * 64 Refresh cycle in ms per number of rows
463 * --------------------------------------------
464 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
466 * 50 MHz => 50.000.000 / Divider = 98
467 * 66 Mhz => 66.000.000 / Divider = 129
468 * 80 Mhz => 80.000.000 / Divider = 156
470 #if defined(CONFIG_80MHz)
471 #define CFG_MAMR_PTA 156
472 #elif defined(CONFIG_66MHz)
473 #define CFG_MAMR_PTA 129
475 #define CFG_MAMR_PTA 98
476 #endif /*CONFIG_??MHz */
479 * For 16 MBit, refresh rates could be 31.3 us
480 * (= 64 ms / 2K = 125 / quad bursts).
481 * For a simpler initialization, 15.6 us is used instead.
483 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
484 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
486 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
487 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
489 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
490 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
491 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
494 * MAMR settings for SDRAM
498 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
499 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
500 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
502 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
503 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
504 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
508 * Internal Definitions
512 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
513 #define BOOTFLAG_WARM 0x02 /* Software reboot */
515 #endif /* __CONFIG_H */