sunxi: Add support for using MII phy-s with the GMAC nic
[oweals/u-boot.git] / include / configs / bluestone.h
1 /*
2  * bluestone.h - configuration for Bluestone (APM821XX)
3  *
4  * Copyright (c) 2010, Applied Micro Circuits Corporation
5  * Author: Tirumala R Marri <tmarri@apm.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 /*
14  * High Level Configuration Options
15  */
16 #define CONFIG_APM821XX         1       /* APM821XX series    */
17 #define CONFIG_HOSTNAME         bluestone
18
19 #define CONFIG_440              1
20
21 #ifndef CONFIG_SYS_TEXT_BASE
22 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
23 #endif
24
25 /*
26  * Include common defines/options for all AMCC eval boards
27  */
28 #include "amcc-common.h"
29 #define CONFIG_SYS_CLK_FREQ     50000000
30
31 #define CONFIG_BOARD_TYPES              1       /* support board types */
32 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_early_init_f */
33 #define CONFIG_MISC_INIT_R              1       /* Call misc_init_r */
34
35 /*
36  * Base addresses -- Note these are effective addresses where the
37  * actual resources get mapped (not physical addresses)
38  */
39 /* EBC stuff */
40 /* later mapped to this addr */
41 #define CONFIG_SYS_FLASH_BASE           0xFFF00000
42 #define CONFIG_SYS_FLASH_SIZE           (4 << 20)       /* 1MB usable */
43
44 /* EBC Boot Space: 0xFF000000 */
45 #define CONFIG_SYS_BOOT_BASE_ADDR       0xFF000000
46 #define CONFIG_SYS_OCM_BASE             0xE3000000 /* OCM: 32k             */
47 #define CONFIG_SYS_SRAM_BASE            0xE8000000 /* SRAM: 256k           */
48 #define CONFIG_SYS_AHB_BASE             0xE2000000 /* internal AHB peripherals*/
49
50 #define CONFIG_SYS_SRAM_SIZE            (256 << 10)
51 /*
52  * Initial RAM & stack pointer (placed in OCM)
53  */
54 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM    */
55 #define CONFIG_SYS_INIT_RAM_SIZE                (4 << 10)
56 #define CONFIG_SYS_GBL_DATA_OFFSET      \
57         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
58 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
59
60 /*
61  * Environment
62  */
63 /*
64  * Define here the location of the environment variables (FLASH).
65  */
66 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
67
68 /*
69  * FLASH related
70  */
71 #define CONFIG_SYS_FLASH_CFI    /* The flash is CFI compatible  */
72 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver        */
73 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_8BIT
74 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
75 /* max number of memory banks           */
76 #define CONFIG_SYS_MAX_FLASH_BANKS      1
77 /* max number of sectors on one chip    */
78 #define CONFIG_SYS_MAX_FLASH_SECT       80
79 /* Timeout for Flash Erase (in ms)      */
80 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000
81 /* Timeout for Flash Write (in ms)      */
82 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
83 /* use buffered writes (20x faster)     */
84 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
85 /* print 'E' for empty sector on flinfo */
86 #define CONFIG_SYS_FLASH_EMPTY_INFO
87 #ifdef CONFIG_ENV_IS_IN_FLASH
88 #define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector  */
89 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
90 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector   */
91 /* Address and size of Redundant Environment Sector     */
92 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
93 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
94 #endif /* CONFIG_ENV_IS_IN_FLASH */
95
96 /* SDRAM */
97 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
98 #define SPD_EEPROM_ADDRESS      {0x53, 0x51}    /* SPD i2c spd addresses */
99 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration */
100 #define CONFIG_AUTOCALIB        "silent\0"      /* default is non-verbose    */
101 #define CONFIG_DDR_ECC          1       /* with ECC support             */
102
103 /*
104  * Serial Port
105  */
106 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
107
108 /*
109  * I2C
110  */
111 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
112 #define CONFIG_SYS_I2C_MULTI_EEPROMS
113 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
114 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
115 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
116 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5       /* Data sheet */
117
118 /* I2C bootstrap EEPROM */
119 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
120 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
121 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
122
123 /*
124  * Ethernet
125  */
126 #define CONFIG_IBM_EMAC4_V4     1
127 #define CONFIG_EMAC_PHY_MODE    EMAC_PHY_MODE_NONE_RGMII
128 #define CONFIG_HAS_ETH0
129 /* PHY address, See schematics  */
130 #define CONFIG_PHY_ADDR                 0x1f
131 /* reset phy upon startup       */
132 #define CONFIG_PHY_RESET                1
133 /* Include GbE speed/duplex detection */
134 #define CONFIG_PHY_GIGE                 1
135 #define CONFIG_PHY_DYNAMIC_ANEG         1
136
137 /*
138  * External Bus Controller (EBC) Setup
139  **/
140 #define CONFIG_SYS_EBC_CFG      (EBC_CFG_LE_LOCK    |   \
141                                  EBC_CFG_PTD_ENABLE   | \
142                                  EBC_CFG_RTC_2048PERCLK | \
143                                  EBC_CFG_ATC_HI | \
144                                  EBC_CFG_DTC_HI | \
145                                  EBC_CFG_CTC_HI | \
146                                  EBC_CFG_OEO_PREVIOUS)
147 /* NOR Flash */
148 #define CONFIG_SYS_EBC_PB0AP    (EBC_BXAP_BME_DISABLED   | \
149                                 EBC_BXAP_TWT_ENCODE(64)  | \
150                                 EBC_BXAP_BCE_DISABLE    | \
151                                 EBC_BXAP_BCT_2TRANS     | \
152                                 EBC_BXAP_CSN_ENCODE(1)  | \
153                                 EBC_BXAP_OEN_ENCODE(2)  | \
154                                 EBC_BXAP_WBN_ENCODE(2)  | \
155                                 EBC_BXAP_WBF_ENCODE(2)  | \
156                                 EBC_BXAP_TH_ENCODE(7)   | \
157                                 EBC_BXAP_SOR_DELAYED    | \
158                                 EBC_BXAP_BEM_WRITEONLY  | \
159                                 EBC_BXAP_PEN_DISABLED)
160 /* Peripheral Bank Configuration Register - EBC_BxCR */
161 #define CONFIG_SYS_EBC_PB0CR    \
162                         (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
163                         EBC_BXCR_BS_1MB                | \
164                         EBC_BXCR_BU_RW                  | \
165                         EBC_BXCR_BW_8BIT)
166
167
168 #endif /* __CONFIG_H */