2 * U-boot - Configuration file for BF537 STAMP board
5 #ifndef __CONFIG_BF537_STAMP_H__
6 #define __CONFIG_BF537_STAMP_H__
8 #include <asm/config-pre.h>
14 #define CONFIG_BFIN_CPU bf537-0.2
15 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
23 /* CONFIG_CLKIN_HZ is any value in Hz */
24 #define CONFIG_CLKIN_HZ 25000000
25 /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
27 #define CONFIG_CLKIN_HALF 0
28 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
30 #define CONFIG_PLL_BYPASS 0
31 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32 /* Values can range from 0-63 (where 0 means 64) */
33 #define CONFIG_VCO_MULT 20
34 /* CCLK_DIV controls the core clock divider */
35 /* Values can be 1, 2, 4, or 8 ONLY */
36 #define CONFIG_CCLK_DIV 1
37 /* SCLK_DIV controls the system clock divider */
38 /* Values can range from 1-15 */
39 #define CONFIG_SCLK_DIV 4
45 #define CONFIG_MEM_ADD_WDTH 10
46 #define CONFIG_MEM_SIZE 64
48 #define CONFIG_EBIU_SDRRC_VAL 0x306
49 #define CONFIG_EBIU_SDGCTL_VAL 0x91114d
51 #define CONFIG_EBIU_AMGCTL_VAL 0xFF
52 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
53 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
55 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
56 #define CONFIG_SYS_MALLOC_LEN (384 * 1024)
63 #define ADI_CMDS_NETWORK 1
64 #define CONFIG_BFIN_MAC
65 #define CONFIG_NETCONSOLE 1
66 #define CONFIG_NET_MULTI 1
68 #define CONFIG_HOSTNAME bf537-stamp
69 /* Uncomment next line to use fixed MAC address */
70 /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
76 #define CONFIG_FLASH_CFI_DRIVER
77 #define CONFIG_SYS_FLASH_BASE 0x20000000
78 #define CONFIG_SYS_FLASH_CFI
79 #define CONFIG_SYS_FLASH_PROTECTION
80 #define CONFIG_SYS_MAX_FLASH_BANKS 1
81 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
82 #define CONFIG_SYS_MAX_FLASH_SECT 71
88 #define CONFIG_BFIN_SPI
89 #define CONFIG_ENV_SPI_MAX_HZ 30000000
90 #define CONFIG_SF_DEFAULT_SPEED 30000000
91 #define CONFIG_SPI_FLASH
92 #define CONFIG_SPI_FLASH_ATMEL
93 #define CONFIG_SPI_FLASH_SPANSION
94 #define CONFIG_SPI_FLASH_STMICRO
95 #define CONFIG_SPI_FLASH_WINBOND
99 * Env Storage Settings
101 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
102 #define CONFIG_ENV_IS_IN_SPI_FLASH
103 #define CONFIG_ENV_OFFSET 0x10000
104 #define CONFIG_ENV_SIZE 0x2000
105 #define CONFIG_ENV_SECT_SIZE 0x10000
107 #define CONFIG_ENV_IS_IN_FLASH
108 #define CONFIG_ENV_OFFSET 0x4000
109 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
110 #define CONFIG_ENV_SIZE 0x2000
111 #define CONFIG_ENV_SECT_SIZE 0x2000
113 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
114 #define ENV_IS_EMBEDDED
116 #define ENV_IS_EMBEDDED_CUSTOM
118 #ifdef ENV_IS_EMBEDDED
119 /* WARNING - the following is hand-optimized to fit within
120 * the sector before the environment sector. If it throws
121 * an error during compilation remove an object here to get
122 * it linked after the configuration sector.
124 # define LDS_BOARD_TEXT \
125 cpu/blackfin/traps.o (.text .text.*); \
126 cpu/blackfin/interrupt.o (.text .text.*); \
127 cpu/blackfin/serial.o (.text .text.*); \
128 common/dlmalloc.o (.text .text.*); \
129 lib_generic/crc32.o (.text .text.*); \
130 . = DEFINED(env_offset) ? env_offset : .; \
131 common/env_embedded.o (.text .text.*);
138 #define CONFIG_BFIN_TWI_I2C 1
139 #define CONFIG_HARD_I2C 1
140 #define CONFIG_SYS_I2C_SPEED 50000
141 #define CONFIG_SYS_I2C_SLAVE 0
148 #define CONFIG_BFIN_SPI_MMC
154 /* #define CONFIG_BF537_NAND */
155 #ifdef CONFIG_BF537_NAND
156 # define CONFIG_CMD_NAND
159 #define CONFIG_SYS_NAND_ADDR 0x20212000
160 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND_ADDR
161 #define CONFIG_SYS_MAX_NAND_DEVICE 1
162 #define SECTORSIZE 512
163 #define ADDR_COLUMN 1
165 #define ADDR_COLUMN_PAGE 3
166 #define NAND_ChipID_UNKNOWN 0x00
167 #define NAND_MAX_FLOORS 1
168 #define BFIN_NAND_READY PF3
170 #define NAND_WAIT_READY(nand) \
173 while (!(*pPORTFIO & PF3)) \
174 if (timeout++ > 100000) \
178 #define BFIN_NAND_CLE (1 << 2) /* A2 -> Command Enable */
179 #define BFIN_NAND_ALE (1 << 1) /* A1 -> Address Enable */
180 #define WRITE_NAND_COMMAND(d, adr) bfin_write8(adr | BFIN_NAND_CLE, d)
181 #define WRITE_NAND_ADDRESS(d, adr) bfin_write8(adr | BFIN_NAND_ALE, d)
182 #define WRITE_NAND(d, adr) bfin_write8(adr, d)
183 #define READ_NAND(adr) bfin_read8(adr)
187 * CF-CARD IDE-HDD Support
189 /* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
190 /* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
191 /* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
193 #if defined(CONFIG_BFIN_CF_IDE) || \
194 defined(CONFIG_BFIN_HDD_IDE) || \
195 defined(CONFIG_BFIN_TRUE_IDE)
196 # define CONFIG_BFIN_IDE 1
197 # define CONFIG_CMD_IDE
200 #if defined(CONFIG_BFIN_IDE)
202 #define CONFIG_DOS_PARTITION 1
206 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
207 #undef CONFIG_IDE_LED /* no led for ide supported */
208 #undef CONFIG_IDE_RESET /* no reset for ide supported */
210 #define CONFIG_SYS_IDE_MAXBUS 1
211 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
213 #undef CONFIG_EBIU_AMBCTL1_VAL
214 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
216 #define CONFIG_CF_ATASEL_DIS 0x20311800
217 #define CONFIG_CF_ATASEL_ENA 0x20311802
219 #if defined(CONFIG_BFIN_TRUE_IDE)
221 * Note that these settings aren't for the most part used in include/ata.h
222 * when all of the ATA registers are setup
224 #define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
225 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
226 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
227 #define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
228 #define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
229 #define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
231 #elif defined(CONFIG_BFIN_CF_IDE)
232 #define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
233 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
234 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */
235 #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */
236 #define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */
237 #define CONFIG_SYS_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
239 #elif defined(CONFIG_BFIN_HDD_IDE)
240 #define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
241 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
242 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
243 #define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
244 #define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
245 #define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
246 #undef CONFIG_SCLK_DIV
247 #define CONFIG_SCLK_DIV 8
256 #define CONFIG_MISC_INIT_R
257 #define CONFIG_RTC_BFIN
258 #define CONFIG_UART_CONSOLE 0
260 /* #define CONFIG_BF537_STAMP_LEDCMD 1 */
262 /* Define if want to do post memory test */
265 #define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
266 #define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
271 * Pull in common ADI header for remaining command/environment setup
273 #include <configs/bfin_adi_common.h>