2 * U-boot - Configuration file for BF533 STAMP board
5 #ifndef __CONFIG_STAMP_H__
6 #define __CONFIG_STAMP_H__
8 #include <asm/blackfin-config-pre.h>
10 #define CONFIG_STAMP 1
11 #define CONFIG_RTC_BFIN 1
12 #define CONFIG_BF533 1
15 * Blackfin can support several boot modes
17 #define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
18 #define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
19 #define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
20 /* Define the boot mode */
21 #define BFIN_BOOT_MODE BF533_BYPASS_BOOT
22 /* #define BFIN_BOOT_MODE BF533_SPI_BOOT */
24 #define CONFIG_PANIC_HANG 1
26 #define CONFIG_BFIN_CPU bf533-0.3
28 /* This sets the default state of the cache on U-Boot's boot */
29 #define CONFIG_ICACHE_ON
30 #define CONFIG_DCACHE_ON
32 /* Define where the uboot will be loaded by on-chip boot rom */
33 #define APP_ENTRY 0x00001000
36 * Stringize definitions - needed for environmental settings
38 #define STRINGIZE2(x) #x
39 #define STRINGIZE(x) STRINGIZE2(x)
44 #define CONFIG_DRIVER_SMC91111 1
45 #define CONFIG_SMC91111_BASE 0x20300300
47 /* FLASH/ETHERNET uses the same address range */
48 #define SHARED_RESOURCES 1
50 /* Is I2C bit-banged? */
51 #define CONFIG_SOFT_I2C 1
54 * Software (bit-bang) I2C driver configuration
60 * Video splash screen support
62 #define CONFIG_VIDEO 0
70 /* CONFIG_CLKIN_HZ is any value in Hz */
71 #define CONFIG_CLKIN_HZ 11059200
72 /* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
74 #define CONFIG_CLKIN_HALF 0
75 /* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
77 #define CONFIG_PLL_BYPASS 0
78 /* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
79 /* Values can range from 1-64 */
80 #define CONFIG_VCO_MULT 36
81 /* CONFIG_CCLK_DIV controls what the core clock divider is */
82 /* Values can be 1, 2, 4, or 8 ONLY */
83 #define CONFIG_CCLK_DIV 1
84 /* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
85 /* Values can range from 1-15 */
86 #define CONFIG_SCLK_DIV 5
87 /* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
88 /* Values can range from 2-65535 */
89 /* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
90 #define CONFIG_SPI_BAUD 2
92 #if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
93 #define CONFIG_SPI_BAUD_INITBLOCK 4
100 #if (CONFIG_DRIVER_SMC91111)
105 /* network support */
106 #define CONFIG_IPADDR 192.168.0.15
107 #define CONFIG_NETMASK 255.255.255.0
108 #define CONFIG_GATEWAYIP 192.168.0.1
109 #define CONFIG_SERVERIP 192.168.0.2
110 #define CONFIG_HOSTNAME STAMP
111 #define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
113 /* To remove hardcoding and enable MAC storage in EEPROM */
114 /* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
115 #endif /* CONFIG_DRIVER_SMC91111 */
121 #define CFG_FLASH_CFI /* The flash is CFI compatible */
122 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
123 #define CFG_FLASH_CFI_AMD_RESET
125 #define CFG_FLASH_BASE 0x20000000
126 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
127 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
129 #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
130 #define CFG_ENV_IS_IN_FLASH 1
131 #define CFG_ENV_ADDR 0x20004000
132 #define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
133 #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
134 #define CFG_ENV_IS_IN_EEPROM 1
135 #define CFG_ENV_OFFSET 0x4000
136 #define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */
139 #define CFG_ENV_SIZE 0x2000
140 #define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
141 #define ENV_IS_EMBEDDED
143 #define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
144 #define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
145 #define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
147 /* JFFS Partition offset set */
148 #define CFG_JFFS2_FIRST_BANK 0
149 #define CFG_JFFS2_NUM_BANKS 1
150 /* 512k reserved for u-boot */
151 #define CFG_JFFS2_FIRST_SECTOR 11
154 * following timeouts shall be used once the
155 * Flash real protection is enabled
157 #define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
158 #define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
161 * SDRAM settings & memory map
164 #define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
165 #define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
166 #define CONFIG_MEM_MT48LC64M4A2FB_7E 1
168 #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
169 #define CFG_MEMTEST_START 0x00000000 /* memtest works on */
170 #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
171 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
174 #define CFG_SDRAM_BASE 0x00000000
176 #define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024)
177 #define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1)
178 #define CONFIG_LOADADDR 0x01000000
180 #define CFG_LOAD_ADDR CONFIG_LOADADDR
181 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
182 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
183 #define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */
184 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
186 #define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - 0x40000)
187 #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
188 #define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
189 #define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
191 /* Check to make sure everything fits in SDRAM */
192 #if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
193 #error Memory Map does not fit into configuration
196 #if ( CONFIG_CLKIN_HALF == 0 )
197 #define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
199 #define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
202 #if (CONFIG_PLL_BYPASS == 0)
203 #define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
204 #define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
206 #define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
207 #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
210 #if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
211 #if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
212 #define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
214 #undef CONFIG_SPI_FLASH_FAST_READ
222 #define CFG_LONGHELP 1
223 #define CONFIG_CMDLINE_EDITING 1
225 #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
226 #define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
229 /* configuration lookup from the BOOTP/DHCP server, */
230 /* but not try to load any image using TFTP */
232 #define CONFIG_BOOTDELAY 5
233 #define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
234 #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
235 #define CONFIG_BOOTCOMMAND "run ramboot"
236 #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
237 #define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000"
240 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
243 #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
244 #if (CONFIG_DRIVER_SMC91111)
245 #define CONFIG_EXTRA_ENV_SETTINGS \
246 "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
247 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
248 "$(rootpath) console=ttyBF0,57600\0" \
249 "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
250 "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
251 "ramboot=tftpboot $(loadaddr) linux; " \
252 "run ramargs;run addip;bootelf\0" \
253 "nfsboot=tftpboot $(loadaddr) linux; " \
254 "run nfsargs;run addip;bootelf\0" \
255 "flashboot=bootm 0x20100000\0" \
256 "update=tftpboot $(loadaddr) u-boot.bin; " \
257 "protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
258 "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
261 #define CONFIG_EXTRA_ENV_SETTINGS \
262 "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
263 "flashboot=bootm 0x20100000\0" \
267 #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
268 #define CONFIG_EXTRA_ENV_SETTINGS \
269 "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
270 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
271 "$(rootpath) console=ttyBF0,57600\0" \
272 "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
273 "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
274 "ramboot=tftpboot $(loadaddr) linux; " \
275 "run ramargs;run addip;bootelf\0" \
276 "nfsboot=tftpboot $(loadaddr) linux; " \
277 "run nfsargs;run addip;bootelf\0" \
278 "flashboot=bootm 0x20100000\0" \
279 "update=tftpboot $(loadaddr) u-boot.ldr;" \
280 "eeprom write $(loadaddr) 0x0 $(filesize);\0"\
284 #ifdef CONFIG_SOFT_I2C
285 #if (!CONFIG_SOFT_I2C)
286 #undef CONFIG_SOFT_I2C
294 #define CONFIG_BOOTP_BOOTFILESIZE
295 #define CONFIG_BOOTP_BOOTPATH
296 #define CONFIG_BOOTP_GATEWAY
297 #define CONFIG_BOOTP_HOSTNAME
301 * Command line configuration.
303 #include <config_cmd_default.h>
305 #define CONFIG_CMD_ELF
306 #define CONFIG_CMD_CACHE
307 #define CONFIG_CMD_JFFS2
308 #define CONFIG_CMD_EEPROM
309 #define CONFIG_CMD_DATE
311 #if (CONFIG_DRIVER_SMC91111)
312 #define CONFIG_CMD_PING
315 #if (CONFIG_SOFT_I2C)
316 #define CONFIG_CMD_I2C
319 #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
320 #define CONFIG_CMD_DHCP
328 #define CONFIG_BAUDRATE 57600
329 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
331 #define CFG_PROMPT "bfin> " /* Monitor Command Prompt */
333 #if defined(CONFIG_CMD_KGDB)
334 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
336 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
338 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
339 #define CFG_MAXARGS 16 /* max number of command args */
340 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
342 #define CONFIG_LOADS_ECHO 1
346 * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
348 #if (CONFIG_SOFT_I2C)
350 #define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
351 #define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
352 #define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
353 #define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
354 #define I2C_SDA(bit) if(bit) { \
355 *pFIO_FLAG_S = PF_SDA; \
359 *pFIO_FLAG_C = PF_SDA; \
362 #define I2C_SCL(bit) if(bit) { \
363 *pFIO_FLAG_S = PF_SCL; \
367 *pFIO_FLAG_C = PF_SCL; \
370 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
372 #define CFG_I2C_SPEED 50000
373 #define CFG_I2C_SLAVE 0xFE
374 #endif /* CONFIG_SOFT_I2C */
377 * Compact Flash settings
380 /* Enabled below option for CF support */
381 /* #define CONFIG_STAMP_CF 1 */
383 #if defined(CONFIG_STAMP_CF) && defined(CONFIG_CMD_IDE)
385 #define CONFIG_MISC_INIT_R 1
386 #define CONFIG_DOS_PARTITION 1
390 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
391 #undef CONFIG_IDE_LED /* no led for ide supported */
392 #undef CONFIG_IDE_RESET /* no reset for ide supported */
394 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
395 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
397 #define CFG_ATA_BASE_ADDR 0x20200000
398 #define CFG_ATA_IDE0_OFFSET 0x0000
400 #define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
401 #define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
402 #define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
404 #define CFG_ATA_STRIDE 2
408 * Miscellaneous configurable options
411 #define CFG_HZ 1000 /* 1ms time tick */
413 #define CFG_BOOTM_LEN 0x4000000/* Large Image Length, set to 64 Meg */
415 #define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
421 #define CONFIG_SPLASH_SCREEN 1
422 #define CONFIG_SILENT_CONSOLE 1
429 * FLASH organization and environment definitions
431 #define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */
433 /* 0xFF, 0xBBC3BBc3, 0x99B39983 */
434 /*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
435 #define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
436 B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
437 #define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
438 B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
440 #define AMGCTLVAL 0xFF
441 #define AMBCTL0VAL 0xBBC3BBC3
442 #define AMBCTL1VAL 0x99B39983
443 #define CF_AMBCTL1VAL 0x99B3ffc2
446 #define ET_EXEC_VDSP 0x8
447 #define SHT_STRTAB_VDSP 0x1
448 #define ELFSHDRSIZE_VDSP 0x2C
449 #define VDSP_ENTRY_ADDR 0xFFA00000