ARMV7: AM3517/05: Add support for CraneBoard.
[oweals/u-boot.git] / include / configs / bf518f-ezbrd.h
1 /*
2  * U-boot - Configuration file for BF518F EZBrd board
3  */
4
5 #ifndef __CONFIG_BF518F_EZBRD_H__
6 #define __CONFIG_BF518F_EZBRD_H__
7
8 #include <asm/config-pre.h>
9
10
11 /*
12  * Processor Settings
13  */
14 #define CONFIG_BFIN_CPU             bf518-0.0
15 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
16
17
18 /*
19  * Clock Settings
20  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22  */
23 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
24 #define CONFIG_CLKIN_HZ                 25000000
25 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
26 /*                                                1 = CLKIN / 2         */
27 #define CONFIG_CLKIN_HALF               0
28 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
29 /*                                                1 = bypass PLL        */
30 #define CONFIG_PLL_BYPASS               0
31 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
32 /* Values can range from 0-63 (where 0 means 64)                        */
33 #define CONFIG_VCO_MULT                 16
34 /* CCLK_DIV controls the core clock divider                             */
35 /* Values can be 1, 2, 4, or 8 ONLY                                     */
36 #define CONFIG_CCLK_DIV                 1
37 /* SCLK_DIV controls the system clock divider                           */
38 /* Values can range from 1-15                                           */
39 #define CONFIG_SCLK_DIV                 5
40
41
42 /*
43  * Memory Settings
44  */
45 /* This board has a 64meg MT48H32M16 */
46 #define CONFIG_MEM_ADD_WDTH     10
47 #define CONFIG_MEM_SIZE         64
48
49 #define CONFIG_EBIU_SDRRC_VAL   0x0096
50 #define CONFIG_EBIU_SDGCTL_VAL  (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
51
52 #define CONFIG_EBIU_AMGCTL_VAL  (AMCKEN | AMBEN_ALL)
53 #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
54 #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
55
56 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)
57 #define CONFIG_SYS_MALLOC_LEN   (384 * 1024)
58
59
60 /*
61  * Network Settings
62  */
63 #if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
64 #define ADI_CMDS_NETWORK        1
65 #define CONFIG_BFIN_MAC
66 #define CONFIG_BFIN_MAC_PINS \
67         { \
68         P_MII0_ETxD0, \
69         P_MII0_ETxD1, \
70         P_MII0_ETxD2, \
71         P_MII0_ETxD3, \
72         P_MII0_ETxEN, \
73         P_MII0_TxCLK, \
74         P_MII0_PHYINT, \
75         P_MII0_COL, \
76         P_MII0_ERxD0, \
77         P_MII0_ERxD1, \
78         P_MII0_ERxD2, \
79         P_MII0_ERxD3, \
80         P_MII0_ERxDV, \
81         P_MII0_ERxCLK, \
82         P_MII0_CRS, \
83         P_MII0_MDC, \
84         P_MII0_MDIO, \
85         0 }
86 #define CONFIG_NETCONSOLE       1
87 #define CONFIG_NET_MULTI        1
88 #endif
89 #define CONFIG_HOSTNAME         bf518f-ezbrd
90 #define CONFIG_PHY_ADDR         3
91 /* Uncomment next line to use fixed MAC address */
92 /* #define CONFIG_ETHADDR       02:80:ad:20:31:e8 */
93
94
95 /*
96  * Flash Settings
97  */
98 #define CONFIG_FLASH_CFI_DRIVER
99 #define CONFIG_SYS_FLASH_BASE           0x20000000
100 #define CONFIG_SYS_FLASH_CFI
101 #define CONFIG_SYS_FLASH_PROTECTION
102 #define CONFIG_SYS_MAX_FLASH_BANKS      1
103 #define CONFIG_SYS_MAX_FLASH_SECT       71
104
105
106 /*
107  * SPI Settings
108  */
109 #define CONFIG_BFIN_SPI
110 #define CONFIG_ENV_SPI_MAX_HZ   30000000
111 #define CONFIG_SF_DEFAULT_SPEED 30000000
112 #define CONFIG_SPI_FLASH
113 #define CONFIG_SPI_FLASH_SST
114 #define CONFIG_SPI_FLASH_STMICRO
115
116
117 /*
118  * Env Storage Settings
119  */
120 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
121 #define CONFIG_ENV_IS_IN_SPI_FLASH
122 #define CONFIG_ENV_OFFSET       0x10000
123 #define CONFIG_ENV_SIZE         0x2000
124 #define CONFIG_ENV_SECT_SIZE    0x10000
125 #else
126 #define CONFIG_ENV_IS_IN_FLASH
127 #define CONFIG_ENV_OFFSET       0x4000
128 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
129 #define CONFIG_ENV_SIZE         0x2000
130 #define CONFIG_ENV_SECT_SIZE    0x2000
131 #endif
132 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
133
134
135 /*
136  * I2C Settings
137  */
138 #define CONFIG_BFIN_TWI_I2C     1
139 #define CONFIG_HARD_I2C         1
140
141
142 /*
143  * SDH Settings
144  */
145 #if !defined(__ADSPBF512__)
146 #define CONFIG_GENERIC_MMC
147 #define CONFIG_MMC
148 #define CONFIG_BFIN_SDH
149 #endif
150
151
152 /*
153  * Misc Settings
154  */
155 #define CONFIG_BOARD_EARLY_INIT_F
156 #define CONFIG_MISC_INIT_R
157 #define CONFIG_RTC_BFIN
158 #define CONFIG_UART_CONSOLE     0
159
160
161 /*
162  * Pull in common ADI header for remaining command/environment setup
163  */
164 #include <configs/bfin_adi_common.h>
165
166 #endif