3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37 #define CONFIG_ATC 1 /* ...on a ATC board */
40 * select serial console configuration
42 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
43 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
46 * if CONFIG_CONS_NONE is defined, then the serial console routines must
47 * defined elsewhere (for example, on the cogent platform, there are serial
48 * ports on the motherboard which are used for the serial console - see
49 * cogent/cma101/serial.[ch]).
51 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
52 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
53 #undef CONFIG_CONS_NONE /* define if console on something else*/
54 #define CONFIG_CONS_INDEX 2 /* which serial channel for console */
56 #define CONFIG_BAUDRATE 115200
59 * select ethernet configuration
61 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
62 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
65 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
66 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
67 * from CONFIG_COMMANDS to remove support for networking.
70 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
71 #undef CONFIG_ETHER_NONE /* define if ether on something else */
72 #define CONFIG_ETHER_ON_FCC
74 #define CONFIG_NET_MULTI
75 #define CONFIG_ETHER_ON_FCC2
80 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
81 * - Enable Full Duplex in FSMR
83 # define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
84 # define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
85 # define CFG_CPMFCR_RAMTYPE 0
86 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
88 #define CONFIG_ETHER_ON_FCC3
93 * - RAM for BD/Buffers is on the local Bus (see 28-13)
94 * - Enable Half Duplex in FSMR
96 # define CFG_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
97 # define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
99 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
100 #define CONFIG_8260_CLKIN 64000000 /* in Hz */
102 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
104 #undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
106 #define CONFIG_PREBOOT \
108 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\
111 #undef CONFIG_BOOTARGS
112 #define CONFIG_BOOTCOMMAND \
114 "setenv bootargs root=/dev/nfs rw " \
115 "nfsroot=$(serverip):$(rootpath) " \
116 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\
119 /*-----------------------------------------------------------------------
120 * Miscellaneous configuration options
123 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
124 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
126 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
128 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
136 #define CONFIG_DOS_PARTITION
138 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
139 #include <cmd_confdefs.h>
142 * Miscellaneous configurable options
144 #define CFG_LONGHELP /* undef to save memory */
145 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
146 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
147 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
149 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
151 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
152 #define CFG_MAXARGS 16 /* max number of command args */
153 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
155 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
156 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
158 #define CFG_LOAD_ADDR 0x100000 /* default load address */
160 #define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
162 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
164 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
166 #define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */
168 #define CFG_ALLOC_DPRAM
170 #undef CONFIG_WATCHDOG /* watchdog disabled */
174 #define CONFIG_RTC_DS12887
176 #define RTC_BASE_ADDR 0xF5000000
177 #define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800
178 #define RTC_PORT_DATA RTC_BASE_ADDR + 0x808
180 #define CONFIG_MISC_INIT_R
183 * For booting Linux, the board info and command line data
184 * have to be in the first 8 MB of memory, since this is
185 * the maximum mapped by the Linux kernel during initialization.
187 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
189 /*-----------------------------------------------------------------------
190 * Flash configuration
193 #define CFG_FLASH_BASE 0xFF000000
194 #define CFG_FLASH_SIZE 0x00800000
196 /*-----------------------------------------------------------------------
199 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
200 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
202 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
203 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
205 #define CONFIG_FLASH_16BIT
207 /*-----------------------------------------------------------------------
208 * Hard Reset Configuration Words
210 * if you change bits in the HRCW, you must also change the CFG_*
211 * defines for the various registers affected by the HRCW e.g. changing
212 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
214 #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
218 /* no slaves so just fill with zeros */
219 #define CFG_HRCW_SLAVE1 0
220 #define CFG_HRCW_SLAVE2 0
221 #define CFG_HRCW_SLAVE3 0
222 #define CFG_HRCW_SLAVE4 0
223 #define CFG_HRCW_SLAVE5 0
224 #define CFG_HRCW_SLAVE6 0
225 #define CFG_HRCW_SLAVE7 0
227 /*-----------------------------------------------------------------------
228 * Internal Memory Mapped Register
230 #define CFG_IMMR 0xF0000000
232 /*-----------------------------------------------------------------------
233 * Definitions for initial stack pointer and data area (in DPRAM)
235 #define CFG_INIT_RAM_ADDR CFG_IMMR
236 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
237 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
238 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
239 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
241 /*-----------------------------------------------------------------------
242 * Start addresses for the final memory configuration
243 * (Set up by the startup code)
244 * Please note that CFG_SDRAM_BASE _must_ start at 0
246 * 60x SDRAM is mapped at CFG_SDRAM_BASE.
248 #define CFG_SDRAM_BASE 0x00000000
249 #define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
250 #define CFG_MONITOR_BASE TEXT_BASE
251 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
252 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
254 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
259 #define CONFIG_PCI_PNP
260 #define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
263 /* environment is in Flash */
264 #define CFG_ENV_IS_IN_FLASH 1
265 # define CFG_ENV_ADDR (CFG_FLASH_BASE+0x30000)
266 # define CFG_ENV_SIZE 0x10000
267 # define CFG_ENV_SECT_SIZE 0x10000
269 #define CFG_ENV_IS_IN_EEPROM 1
270 #define CFG_ENV_OFFSET 0
271 #define CFG_ENV_SIZE 2048
272 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
275 * Internal Definitions
279 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
280 #define BOOTFLAG_WARM 0x02 /* Software reboot */
283 /*-----------------------------------------------------------------------
284 * Cache Configuration
286 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
287 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
288 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
291 /*-----------------------------------------------------------------------
292 * HIDx - Hardware Implementation-dependent Registers 2-11
293 *-----------------------------------------------------------------------
294 * HID0 also contains cache control - initially enable both caches and
295 * invalidate contents, then the final state leaves only the instruction
296 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
297 * but Soft reset does not.
299 * HID1 has only read-only information - nothing to set.
301 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
302 HID0_DCI|HID0_IFEM|HID0_ABE)
303 #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
306 /*-----------------------------------------------------------------------
307 * RMR - Reset Mode Register 5-5
308 *-----------------------------------------------------------------------
309 * turn on Checkstop Reset Enable
311 #define CFG_RMR RMR_CSRE
313 /*-----------------------------------------------------------------------
314 * BCR - Bus Configuration 4-25
315 *-----------------------------------------------------------------------
317 #define BCR_APD01 0x10000000
318 #define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
320 /*-----------------------------------------------------------------------
321 * SIUMCR - SIU Module Configuration 4-31
322 *-----------------------------------------------------------------------
324 #define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_APPC10|\
325 SIUMCR_CS10PC00|SIUMCR_BCTLC10)
327 /*-----------------------------------------------------------------------
328 * SYPCR - System Protection Control 4-35
329 * SYPCR can only be written once after reset!
330 *-----------------------------------------------------------------------
331 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
333 #if defined(CONFIG_WATCHDOG)
334 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
335 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
337 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
338 SYPCR_SWRI|SYPCR_SWP)
339 #endif /* CONFIG_WATCHDOG */
341 /*-----------------------------------------------------------------------
342 * TMCNTSC - Time Counter Status and Control 4-40
343 *-----------------------------------------------------------------------
344 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
345 * and enable Time Counter
347 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
349 /*-----------------------------------------------------------------------
350 * PISCR - Periodic Interrupt Status and Control 4-42
351 *-----------------------------------------------------------------------
352 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
355 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
357 /*-----------------------------------------------------------------------
358 * SCCR - System Clock Control 9-8
359 *-----------------------------------------------------------------------
360 * Ensure DFBRG is Divide by 16
362 #define CFG_SCCR SCCR_DFBRG01
364 /*-----------------------------------------------------------------------
365 * RCCR - RISC Controller Configuration 13-7
366 *-----------------------------------------------------------------------
370 #define CFG_MIN_AM_MASK 0xC0000000
371 /*-----------------------------------------------------------------------
372 * MPTPR - Memory Refresh Timer Prescaler Register 10-18
373 *-----------------------------------------------------------------------
375 #define CFG_MPTPR 0x1F00
377 /*-----------------------------------------------------------------------
378 * PSRT - Refresh Timer Register 10-16
379 *-----------------------------------------------------------------------
381 #define CFG_PSRT 0x0f
383 /*-----------------------------------------------------------------------
384 * PSRT - SDRAM Mode Register 10-10
385 *-----------------------------------------------------------------------
388 /* SDRAM initialization values for 8-column chips
390 #define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
392 ORxS_ROWST_PBI1_A7 |\
395 #define CFG_PSDMR_8COL (PSDMR_PBI |\
396 PSDMR_SDAM_A15_IS_A5 |\
397 PSDMR_BSMA_A15_A17 |\
398 PSDMR_SDA10_PBI1_A7 |\
406 /* SDRAM initialization values for 9-column chips
408 #define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
410 ORxS_ROWST_PBI1_A6 |\
413 #define CFG_PSDMR_9COL (PSDMR_PBI |\
414 PSDMR_SDAM_A16_IS_A5 |\
415 PSDMR_BSMA_A15_A17 |\
416 PSDMR_SDA10_PBI1_A6 |\
425 * Init Memory Controller:
427 * Bank Bus Machine PortSz Device
428 * ---- --- ------- ------ ------
429 * 0 60x GPCM 8 bit Boot ROM
430 * 1 60x GPCM 64 bit FLASH
431 * 2 60x SDRAM 64 bit SDRAM
435 #define CFG_MRS_OFFS 0x00000000
439 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
444 #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
451 /* Bank 2 - 60x bus SDRAM
454 #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
459 #define CFG_OR2_PRELIM CFG_OR2_8COL
461 #define CFG_PSDMR CFG_PSDMR_8COL
462 #endif /* CFG_RAMBOOT */
464 #define CFG_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) |\
469 #define CFG_OR4_PRELIM (ORxU_AM_MSK | ORxU_BI)
471 /*-----------------------------------------------------------------------
473 *-----------------------------------------------------------------------
476 #define CONFIG_I82365
478 #define CFG_PCMCIA_MEM_ADDR 0x81000000
479 #define CFG_PCMCIA_MEM_SIZE 0x1000
481 /*-----------------------------------------------------------------------
482 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
483 *-----------------------------------------------------------------------
486 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
488 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
489 #undef CONFIG_IDE_LED /* LED for ide not supported */
490 #undef CONFIG_IDE_RESET /* reset for ide not supported */
492 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
493 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
495 #define CFG_ATA_IDE0_OFFSET 0x0000
497 #define CFG_ATA_BASE_ADDR 0xa0000000
499 /* Offset for data I/O */
500 #define CFG_ATA_DATA_OFFSET 0x100
502 /* Offset for normal register accesses */
503 #define CFG_ATA_REG_OFFSET 0x100
505 /* Offset for alternate registers */
506 #define CFG_ATA_ALT_OFFSET 0x108
508 #endif /* __CONFIG_H */