2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * Configuation settings for the AT91SAM9263EK board.
8 * SPDX-License-Identifier: GPL-2.0+
15 * SoC must be defined first, before hardware.h is included.
16 * In this case SoC is defined in boards.cfg.
18 #include <asm/hardware.h>
20 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
21 #define CONFIG_SYS_TEXT_BASE 0x21F00000
23 #define CONFIG_SYS_TEXT_BASE 0x0000000
26 /* ARM asynchronous clock */
27 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
30 #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */
32 #define CONFIG_ARCH_CPU_INIT
34 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
35 #define CONFIG_SETUP_MEMORY_TAGS 1
36 #define CONFIG_INITRD_TAG 1
38 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
39 #define CONFIG_SKIP_LOWLEVEL_INIT
41 #define CONFIG_SYS_USE_NORFLASH
47 #define CONFIG_ATMEL_LEGACY
48 #define CONFIG_AT91_GPIO 1
49 #define CONFIG_AT91_GPIO_PULLUP 1
52 #define CONFIG_ATMEL_USART
53 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
54 #define CONFIG_USART_ID ATMEL_ID_SYS
55 #define CONFIG_BAUDRATE 115200
58 #define LCD_BPP LCD_COLOR8
59 #define CONFIG_LCD_LOGO 1
60 #undef LCD_TEST_PATTERN
61 #define CONFIG_LCD_INFO 1
62 #define CONFIG_LCD_INFO_BELOW_LOGO 1
63 #define CONFIG_SYS_WHITE_ON_BLACK 1
64 #define CONFIG_ATMEL_LCD 1
65 #define CONFIG_ATMEL_LCD_BGR555 1
68 #define CONFIG_AT91_LED
69 #define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */
70 #define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */
71 #define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */
77 #define CONFIG_BOOTP_BOOTFILESIZE 1
78 #define CONFIG_BOOTP_BOOTPATH 1
79 #define CONFIG_BOOTP_GATEWAY 1
80 #define CONFIG_BOOTP_HOSTNAME 1
83 * Command line configuration.
85 #define CONFIG_CMD_NAND 1
88 #define CONFIG_NR_DRAM_BANKS 1
89 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
90 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
92 #define CONFIG_SYS_INIT_SP_ADDR \
93 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
96 #define CONFIG_ATMEL_DATAFLASH_SPI
97 #define CONFIG_HAS_DATAFLASH 1
98 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
99 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
100 #define AT91_SPI_CLK 15000000
101 #define DATAFLASH_TCSS (0x1a << 16)
102 #define DATAFLASH_TCHS (0x1 << 24)
105 #ifdef CONFIG_CMD_MMC
106 #define CONFIG_GENERIC_ATMEL_MCI
109 /* NOR flash, if populated */
110 #ifdef CONFIG_SYS_USE_NORFLASH
111 #define CONFIG_SYS_FLASH_CFI 1
112 #define CONFIG_FLASH_CFI_DRIVER 1
113 #define PHYS_FLASH_1 0x10000000
114 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
115 #define CONFIG_SYS_MAX_FLASH_SECT 256
116 #define CONFIG_SYS_MAX_FLASH_BANKS 1
118 #define CONFIG_SYS_MONITOR_SEC 1:0-3
119 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
120 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
121 #define CONFIG_ENV_IS_IN_FLASH 1
122 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000)
123 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
125 /* Address and size of Primary Environment Sector */
126 #define CONFIG_ENV_SIZE 0x10000
128 #define CONFIG_EXTRA_ENV_SETTINGS \
129 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
131 "protect off ${monitor_base} +${filesize};" \
132 "erase ${monitor_base} +${filesize};" \
133 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \
134 "protect on ${monitor_base} +${filesize}\0"
136 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
137 #define MASTER_PLL_MUL 171
138 #define MASTER_PLL_DIV 14
139 #define MASTER_PLL_OUT 3
142 #define CONFIG_SYS_MOR_VAL \
143 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
144 #define CONFIG_SYS_PLLAR_VAL \
145 (AT91_PMC_PLLAR_29 | \
146 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
147 AT91_PMC_PLLXR_PLLCOUNT(63) | \
148 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
149 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
151 /* PCK/2 = MCK Master Clock from PLLA */
152 #define CONFIG_SYS_MCKR1_VAL \
153 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
154 AT91_PMC_MCKR_MDIV_2)
156 /* PCK/2 = MCK Master Clock from PLLA */
157 #define CONFIG_SYS_MCKR2_VAL \
158 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
159 AT91_PMC_MCKR_MDIV_2)
161 /* define PDC[31:16] as DATA[31:16] */
162 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
163 /* no pull-up for D[31:16] */
164 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
165 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
166 #define CONFIG_SYS_MATRIX_EBICSA_VAL \
167 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
168 AT91_MATRIX_CSA_EBI_CS1A)
171 /* SDRAMC_MR Mode register */
172 #define CONFIG_SYS_SDRC_MR_VAL1 0
173 /* SDRAMC_TR - Refresh Timer register */
174 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C
175 /* SDRAMC_CR - Configuration register*/
176 #define CONFIG_SYS_SDRC_CR_VAL \
177 (AT91_SDRAMC_NC_9 | \
178 AT91_SDRAMC_NR_13 | \
180 AT91_SDRAMC_CAS_3 | \
181 AT91_SDRAMC_DBW_32 | \
182 (1 << 8) | /* Write Recovery Delay */ \
183 (7 << 12) | /* Row Cycle Delay */ \
184 (2 << 16) | /* Row Precharge Delay */ \
185 (2 << 20) | /* Row to Column Delay */ \
186 (5 << 24) | /* Active to Precharge Delay */ \
187 (1 << 28)) /* Exit Self Refresh to Active Delay */
189 /* Memory Device Register -> SDRAM */
190 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
191 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
192 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
193 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
194 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
195 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
196 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
197 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
198 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
199 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
200 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
201 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
202 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
203 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
204 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
205 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
206 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
207 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
209 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
210 #define CONFIG_SYS_SMC0_SETUP0_VAL \
211 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
212 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
213 #define CONFIG_SYS_SMC0_PULSE0_VAL \
214 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
215 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
216 #define CONFIG_SYS_SMC0_CYCLE0_VAL \
217 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
218 #define CONFIG_SYS_SMC0_MODE0_VAL \
219 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
220 AT91_SMC_MODE_DBW_16 | \
221 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
223 /* user reset enable */
224 #define CONFIG_SYS_RSTC_RMR_VAL \
226 AT91_RSTC_MR_URSTEN | \
227 AT91_RSTC_MR_ERSTL(15))
229 /* Disable Watchdog */
230 #define CONFIG_SYS_WDTC_WDMR_VAL \
231 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
232 AT91_WDT_MR_WDV(0xfff) | \
233 AT91_WDT_MR_WDDIS | \
234 AT91_WDT_MR_WDD(0xfff))
240 #ifdef CONFIG_CMD_NAND
241 #define CONFIG_NAND_ATMEL
242 #define CONFIG_SYS_MAX_NAND_DEVICE 1
243 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
244 #define CONFIG_SYS_NAND_DBW_8 1
245 /* our ALE is AD21 */
246 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
247 /* our CLE is AD22 */
248 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
249 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
250 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
254 #define CONFIG_MACB 1
255 #define CONFIG_RMII 1
256 #define CONFIG_NET_RETRY_COUNT 20
257 #define CONFIG_RESET_PHY_R 1
258 #define CONFIG_AT91_WANTS_COMMON_PHY
261 #define CONFIG_USB_ATMEL
262 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
263 #define CONFIG_USB_OHCI_NEW 1
264 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
265 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
266 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
267 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
269 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
271 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
272 #define CONFIG_SYS_MEMTEST_END 0x23e00000
274 #ifdef CONFIG_SYS_USE_DATAFLASH
276 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
277 #define CONFIG_ENV_IS_IN_DATAFLASH 1
278 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
279 #define CONFIG_ENV_OFFSET 0x4200
280 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
281 #define CONFIG_ENV_SIZE 0x4200
282 #define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
283 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
284 "root=/dev/mtdblock0 " \
285 "mtdparts=atmel_nand:-(root) "\
286 "rw rootfstype=jffs2"
288 #elif CONFIG_SYS_USE_NANDFLASH
290 /* bootstrap + u-boot + env + linux in nandflash */
291 #define CONFIG_ENV_IS_IN_NAND 1
292 #define CONFIG_ENV_OFFSET 0xc0000
293 #define CONFIG_ENV_OFFSET_REDUND 0x100000
294 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
295 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
296 #define CONFIG_BOOTARGS \
297 "console=ttyS0,115200 earlyprintk " \
298 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
299 "256k(env),256k(env_redundant),256k(spare)," \
300 "512k(dtb),6M(kernel)ro,-(rootfs) " \
301 "root=/dev/mtdblock7 rw rootfstype=jffs2"
304 #define CONFIG_SYS_CBSIZE 256
305 #define CONFIG_SYS_MAXARGS 16
306 #define CONFIG_SYS_LONGHELP 1
307 #define CONFIG_CMDLINE_EDITING 1
308 #define CONFIG_AUTO_COMPLETE
311 * Size of malloc() pool
313 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)