2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * Configuation settings for the AT91SAM9263EK board.
8 * SPDX-License-Identifier: GPL-2.0+
15 * SoC must be defined first, before hardware.h is included.
16 * In this case SoC is defined in boards.cfg.
18 #include <asm/hardware.h>
20 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
21 #define CONFIG_SYS_TEXT_BASE 0x21F00000
23 #define CONFIG_SYS_TEXT_BASE 0x0000000
26 /* ARM asynchronous clock */
27 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
30 #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */
32 #define CONFIG_ARCH_CPU_INIT
34 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
35 #define CONFIG_SETUP_MEMORY_TAGS 1
36 #define CONFIG_INITRD_TAG 1
38 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
39 #define CONFIG_SKIP_LOWLEVEL_INIT
41 #define CONFIG_SYS_USE_NORFLASH
47 #define CONFIG_ATMEL_LEGACY
48 #define CONFIG_AT91_GPIO 1
49 #define CONFIG_AT91_GPIO_PULLUP 1
52 #define CONFIG_ATMEL_USART
53 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
54 #define CONFIG_USART_ID ATMEL_ID_SYS
57 #define LCD_BPP LCD_COLOR8
58 #define CONFIG_LCD_LOGO 1
59 #undef LCD_TEST_PATTERN
60 #define CONFIG_LCD_INFO 1
61 #define CONFIG_LCD_INFO_BELOW_LOGO 1
62 #define CONFIG_ATMEL_LCD 1
63 #define CONFIG_ATMEL_LCD_BGR555 1
66 #define CONFIG_AT91_LED
67 #define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */
68 #define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */
69 #define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */
75 #define CONFIG_BOOTP_BOOTFILESIZE 1
76 #define CONFIG_BOOTP_BOOTPATH 1
77 #define CONFIG_BOOTP_GATEWAY 1
78 #define CONFIG_BOOTP_HOSTNAME 1
81 * Command line configuration.
83 #define CONFIG_CMD_NAND 1
86 #define CONFIG_NR_DRAM_BANKS 1
87 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
88 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
90 #define CONFIG_SYS_INIT_SP_ADDR \
91 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
94 #define CONFIG_ATMEL_DATAFLASH_SPI
95 #define CONFIG_HAS_DATAFLASH 1
96 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
97 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
98 #define AT91_SPI_CLK 15000000
99 #define DATAFLASH_TCSS (0x1a << 16)
100 #define DATAFLASH_TCHS (0x1 << 24)
103 #ifdef CONFIG_CMD_MMC
104 #define CONFIG_GENERIC_ATMEL_MCI
107 /* NOR flash, if populated */
108 #ifdef CONFIG_SYS_USE_NORFLASH
109 #define CONFIG_SYS_FLASH_CFI 1
110 #define CONFIG_FLASH_CFI_DRIVER 1
111 #define PHYS_FLASH_1 0x10000000
112 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
113 #define CONFIG_SYS_MAX_FLASH_SECT 256
114 #define CONFIG_SYS_MAX_FLASH_BANKS 1
116 #define CONFIG_SYS_MONITOR_SEC 1:0-3
117 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
118 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
119 #define CONFIG_ENV_IS_IN_FLASH 1
120 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000)
121 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
123 /* Address and size of Primary Environment Sector */
124 #define CONFIG_ENV_SIZE 0x10000
126 #define CONFIG_EXTRA_ENV_SETTINGS \
127 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
129 "protect off ${monitor_base} +${filesize};" \
130 "erase ${monitor_base} +${filesize};" \
131 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \
132 "protect on ${monitor_base} +${filesize}\0"
134 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
135 #define MASTER_PLL_MUL 171
136 #define MASTER_PLL_DIV 14
137 #define MASTER_PLL_OUT 3
140 #define CONFIG_SYS_MOR_VAL \
141 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
142 #define CONFIG_SYS_PLLAR_VAL \
143 (AT91_PMC_PLLAR_29 | \
144 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
145 AT91_PMC_PLLXR_PLLCOUNT(63) | \
146 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
147 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
149 /* PCK/2 = MCK Master Clock from PLLA */
150 #define CONFIG_SYS_MCKR1_VAL \
151 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
152 AT91_PMC_MCKR_MDIV_2)
154 /* PCK/2 = MCK Master Clock from PLLA */
155 #define CONFIG_SYS_MCKR2_VAL \
156 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
157 AT91_PMC_MCKR_MDIV_2)
159 /* define PDC[31:16] as DATA[31:16] */
160 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
161 /* no pull-up for D[31:16] */
162 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
163 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
164 #define CONFIG_SYS_MATRIX_EBICSA_VAL \
165 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
166 AT91_MATRIX_CSA_EBI_CS1A)
169 /* SDRAMC_MR Mode register */
170 #define CONFIG_SYS_SDRC_MR_VAL1 0
171 /* SDRAMC_TR - Refresh Timer register */
172 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C
173 /* SDRAMC_CR - Configuration register*/
174 #define CONFIG_SYS_SDRC_CR_VAL \
175 (AT91_SDRAMC_NC_9 | \
176 AT91_SDRAMC_NR_13 | \
178 AT91_SDRAMC_CAS_3 | \
179 AT91_SDRAMC_DBW_32 | \
180 (1 << 8) | /* Write Recovery Delay */ \
181 (7 << 12) | /* Row Cycle Delay */ \
182 (2 << 16) | /* Row Precharge Delay */ \
183 (2 << 20) | /* Row to Column Delay */ \
184 (5 << 24) | /* Active to Precharge Delay */ \
185 (1 << 28)) /* Exit Self Refresh to Active Delay */
187 /* Memory Device Register -> SDRAM */
188 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
189 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
190 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
191 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
192 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
193 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
194 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
195 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
196 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
197 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
198 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
199 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
200 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
201 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
202 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
203 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
204 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
205 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
207 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
208 #define CONFIG_SYS_SMC0_SETUP0_VAL \
209 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
210 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
211 #define CONFIG_SYS_SMC0_PULSE0_VAL \
212 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
213 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
214 #define CONFIG_SYS_SMC0_CYCLE0_VAL \
215 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
216 #define CONFIG_SYS_SMC0_MODE0_VAL \
217 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
218 AT91_SMC_MODE_DBW_16 | \
219 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
221 /* user reset enable */
222 #define CONFIG_SYS_RSTC_RMR_VAL \
224 AT91_RSTC_MR_URSTEN | \
225 AT91_RSTC_MR_ERSTL(15))
227 /* Disable Watchdog */
228 #define CONFIG_SYS_WDTC_WDMR_VAL \
229 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
230 AT91_WDT_MR_WDV(0xfff) | \
231 AT91_WDT_MR_WDDIS | \
232 AT91_WDT_MR_WDD(0xfff))
238 #ifdef CONFIG_CMD_NAND
239 #define CONFIG_NAND_ATMEL
240 #define CONFIG_SYS_MAX_NAND_DEVICE 1
241 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
242 #define CONFIG_SYS_NAND_DBW_8 1
243 /* our ALE is AD21 */
244 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
245 /* our CLE is AD22 */
246 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
247 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
248 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
252 #define CONFIG_MACB 1
253 #define CONFIG_RMII 1
254 #define CONFIG_NET_RETRY_COUNT 20
255 #define CONFIG_RESET_PHY_R 1
256 #define CONFIG_AT91_WANTS_COMMON_PHY
259 #define CONFIG_USB_ATMEL
260 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
261 #define CONFIG_USB_OHCI_NEW 1
262 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
263 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
264 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
265 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
267 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
269 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
270 #define CONFIG_SYS_MEMTEST_END 0x23e00000
272 #ifdef CONFIG_SYS_USE_DATAFLASH
274 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
275 #define CONFIG_ENV_IS_IN_DATAFLASH 1
276 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
277 #define CONFIG_ENV_OFFSET 0x4200
278 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
279 #define CONFIG_ENV_SIZE 0x4200
280 #define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
281 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
282 "root=/dev/mtdblock0 " \
283 "mtdparts=atmel_nand:-(root) "\
284 "rw rootfstype=jffs2"
286 #elif CONFIG_SYS_USE_NANDFLASH
288 /* bootstrap + u-boot + env + linux in nandflash */
289 #define CONFIG_ENV_IS_IN_NAND 1
290 #define CONFIG_ENV_OFFSET 0xc0000
291 #define CONFIG_ENV_OFFSET_REDUND 0x100000
292 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
293 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
294 #define CONFIG_BOOTARGS \
295 "console=ttyS0,115200 earlyprintk " \
296 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
297 "256k(env),256k(env_redundant),256k(spare)," \
298 "512k(dtb),6M(kernel)ro,-(rootfs) " \
299 "root=/dev/mtdblock7 rw rootfstype=jffs2"
302 #define CONFIG_SYS_CBSIZE 256
303 #define CONFIG_SYS_MAXARGS 16
304 #define CONFIG_SYS_LONGHELP 1
305 #define CONFIG_CMDLINE_EDITING 1
306 #define CONFIG_AUTO_COMPLETE
309 * Size of malloc() pool
311 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)