1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
7 * Configuation settings for the AT91SAM9263EK board.
14 * SoC must be defined first, before hardware.h is included.
15 * In this case SoC is defined in boards.cfg.
17 #include <asm/hardware.h>
19 /* ARM asynchronous clock */
20 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
21 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
23 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
24 #define CONFIG_SETUP_MEMORY_TAGS 1
25 #define CONFIG_INITRD_TAG 1
27 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
28 #define CONFIG_SKIP_LOWLEVEL_INIT
30 #define CONFIG_SYS_USE_NORFLASH
36 #define CONFIG_ATMEL_LEGACY
39 #define LCD_BPP LCD_COLOR8
40 #define CONFIG_LCD_LOGO 1
41 #undef LCD_TEST_PATTERN
42 #define CONFIG_LCD_INFO 1
43 #define CONFIG_LCD_INFO_BELOW_LOGO 1
44 #define CONFIG_ATMEL_LCD 1
45 #define CONFIG_ATMEL_LCD_BGR555 1
50 #define CONFIG_BOOTP_BOOTFILESIZE 1
53 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
54 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
56 #define CONFIG_SYS_INIT_SP_ADDR \
57 (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
59 /* NOR flash, if populated */
60 #ifdef CONFIG_SYS_USE_NORFLASH
61 #define PHYS_FLASH_1 0x10000000
62 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
63 #define CONFIG_SYS_MAX_FLASH_SECT 256
64 #define CONFIG_SYS_MAX_FLASH_BANKS 1
66 #define CONFIG_SYS_MONITOR_SEC 1:0-3
67 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
68 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
69 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000)
70 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
72 /* Address and size of Primary Environment Sector */
73 #define CONFIG_ENV_SIZE 0x10000
75 #define CONFIG_EXTRA_ENV_SETTINGS \
76 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
78 "protect off ${monitor_base} +${filesize};" \
79 "erase ${monitor_base} +${filesize};" \
80 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \
81 "protect on ${monitor_base} +${filesize}\0"
83 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
84 #define MASTER_PLL_MUL 171
85 #define MASTER_PLL_DIV 14
86 #define MASTER_PLL_OUT 3
89 #define CONFIG_SYS_MOR_VAL \
90 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
91 #define CONFIG_SYS_PLLAR_VAL \
92 (AT91_PMC_PLLAR_29 | \
93 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
94 AT91_PMC_PLLXR_PLLCOUNT(63) | \
95 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
96 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
98 /* PCK/2 = MCK Master Clock from PLLA */
99 #define CONFIG_SYS_MCKR1_VAL \
100 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
101 AT91_PMC_MCKR_MDIV_2)
103 /* PCK/2 = MCK Master Clock from PLLA */
104 #define CONFIG_SYS_MCKR2_VAL \
105 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
106 AT91_PMC_MCKR_MDIV_2)
108 /* define PDC[31:16] as DATA[31:16] */
109 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
110 /* no pull-up for D[31:16] */
111 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
112 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
113 #define CONFIG_SYS_MATRIX_EBICSA_VAL \
114 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
115 AT91_MATRIX_CSA_EBI_CS1A)
118 /* SDRAMC_MR Mode register */
119 #define CONFIG_SYS_SDRC_MR_VAL1 0
120 /* SDRAMC_TR - Refresh Timer register */
121 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C
122 /* SDRAMC_CR - Configuration register*/
123 #define CONFIG_SYS_SDRC_CR_VAL \
124 (AT91_SDRAMC_NC_9 | \
125 AT91_SDRAMC_NR_13 | \
127 AT91_SDRAMC_CAS_3 | \
128 AT91_SDRAMC_DBW_32 | \
129 (1 << 8) | /* Write Recovery Delay */ \
130 (7 << 12) | /* Row Cycle Delay */ \
131 (2 << 16) | /* Row Precharge Delay */ \
132 (2 << 20) | /* Row to Column Delay */ \
133 (5 << 24) | /* Active to Precharge Delay */ \
134 (1 << 28)) /* Exit Self Refresh to Active Delay */
136 /* Memory Device Register -> SDRAM */
137 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
138 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
139 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
140 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
141 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
142 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
143 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
144 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
145 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
146 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
147 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
148 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
149 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
150 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
151 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
152 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
153 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
154 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
156 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
157 #define CONFIG_SYS_SMC0_SETUP0_VAL \
158 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
159 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
160 #define CONFIG_SYS_SMC0_PULSE0_VAL \
161 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
162 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
163 #define CONFIG_SYS_SMC0_CYCLE0_VAL \
164 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
165 #define CONFIG_SYS_SMC0_MODE0_VAL \
166 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
167 AT91_SMC_MODE_DBW_16 | \
168 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
170 /* user reset enable */
171 #define CONFIG_SYS_RSTC_RMR_VAL \
173 AT91_RSTC_MR_URSTEN | \
174 AT91_RSTC_MR_ERSTL(15))
176 /* Disable Watchdog */
177 #define CONFIG_SYS_WDTC_WDMR_VAL \
178 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
179 AT91_WDT_MR_WDV(0xfff) | \
180 AT91_WDT_MR_WDDIS | \
181 AT91_WDT_MR_WDD(0xfff))
187 #ifdef CONFIG_CMD_NAND
188 #define CONFIG_SYS_MAX_NAND_DEVICE 1
189 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
190 #define CONFIG_SYS_NAND_DBW_8 1
191 /* our ALE is AD21 */
192 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
193 /* our CLE is AD22 */
194 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
195 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
196 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
200 #define CONFIG_RESET_PHY_R 1
201 #define CONFIG_AT91_WANTS_COMMON_PHY
204 #define CONFIG_USB_ATMEL
205 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
206 #define CONFIG_USB_OHCI_NEW 1
207 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
208 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
209 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
210 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
212 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
214 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
215 #define CONFIG_SYS_MEMTEST_END 0x23e00000
217 #ifdef CONFIG_SYS_USE_DATAFLASH
219 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
220 #define CONFIG_ENV_OFFSET 0x4200
221 #define CONFIG_ENV_SIZE 0x4200
222 #define CONFIG_ENV_SECT_SIZE 0x210
223 #define CONFIG_BOOTCOMMAND "sf probe 0; " \
224 "sf read 0x22000000 0x84000 0x294000; " \
227 #elif CONFIG_SYS_USE_NANDFLASH
229 /* bootstrap + u-boot + env + linux in nandflash */
230 #define CONFIG_ENV_OFFSET 0x140000
231 #define CONFIG_ENV_OFFSET_REDUND 0x100000
232 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
233 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
237 * Size of malloc() pool
239 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)