2 * Rick Bronson <rick@efn.org>
4 * Configuration settings for the AT91RM9200DK board.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /* ARM asynchronous clock */
29 #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
30 #define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
31 /* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
33 #define AT91_SLOW_CLOCK 32768 /* slow clock */
35 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */
36 #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
37 #define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
38 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39 #define USE_920T_MMU 1
41 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
42 #define CONFIG_SETUP_MEMORY_TAGS 1
43 #define CONFIG_INITRD_TAG 1
45 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
46 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
48 #define CONFIG_SYS_MC_PUIA_VAL 0x00000000
49 #define CONFIG_SYS_MC_PUP_VAL 0x00000000
50 #define CONFIG_SYS_MC_PUER_VAL 0x00000000
51 #define CONFIG_SYS_MC_ASR_VAL 0x00000000
52 #define CONFIG_SYS_MC_AASR_VAL 0x00000000
53 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
54 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
57 #define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
58 #define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
59 #define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
62 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
63 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
64 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
65 #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
66 #define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
67 #define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
68 #define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
69 #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
70 #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
71 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
72 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
73 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
74 #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
76 #define CONFIG_SKIP_RELOCATE_UBOOT
77 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
79 * Size of malloc() pool
81 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
82 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
84 #define CONFIG_BAUDRATE 115200
90 /* define one of these to choose the DBGU, USART0 or USART1 as console */
95 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
97 #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
99 #define CONFIG_BOOTDELAY 3
100 /* #define CONFIG_ENV_OVERWRITE 1 */
106 #define CONFIG_BOOTP_BOOTFILESIZE
107 #define CONFIG_BOOTP_BOOTPATH
108 #define CONFIG_BOOTP_GATEWAY
109 #define CONFIG_BOOTP_HOSTNAME
113 * Command line configuration.
115 #include <config_cmd_default.h>
117 #define CONFIG_CMD_DHCP
118 #define CONFIG_CMD_MII
119 #define CONFIG_CMD_NAND
121 #define CONFIG_NAND_LEGACY
123 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
124 #define SECTORSIZE 512
126 #define ADDR_COLUMN 1
128 #define ADDR_COLUMN_PAGE 3
130 #define NAND_ChipID_UNKNOWN 0x00
131 #define NAND_MAX_FLOORS 1
133 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
134 #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
136 #include <asm/arch/AT91RM9200.h> /* needed for port definitions */
137 #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
138 #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
140 #define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
142 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
143 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
144 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
145 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
146 /* the following are NOP's in our implementation */
147 #define NAND_CTL_CLRALE(nandptr)
148 #define NAND_CTL_SETALE(nandptr)
149 #define NAND_CTL_CLRCLE(nandptr)
150 #define NAND_CTL_SETCLE(nandptr)
152 #define CONFIG_NR_DRAM_BANKS 1
153 #define PHYS_SDRAM 0x20000000
154 #define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
156 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
157 #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
159 #define CONFIG_DRIVER_ETHER
160 #define CONFIG_NET_RETRY_COUNT 20
161 #define CONFIG_AT91C_USE_RMII
163 /* AC Characteristics */
164 /* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
165 #define DATAFLASH_TCSS (0xC << 16)
166 #define DATAFLASH_TCHS (0x1 << 24)
168 #define CONFIG_HAS_DATAFLASH 1
169 #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
170 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
171 #define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
172 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
173 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
175 #define PHYS_FLASH_1 0x10000000
176 #define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
177 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
178 #define CONFIG_SYS_MAX_FLASH_BANKS 1
179 #define CONFIG_SYS_MAX_FLASH_SECT 256
180 #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
181 #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
183 #undef CONFIG_ENV_IS_IN_DATAFLASH
185 #ifdef CONFIG_ENV_IS_IN_DATAFLASH
186 #define CONFIG_ENV_OFFSET 0x20000
187 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
188 #define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
190 #define CONFIG_ENV_IS_IN_FLASH 1
191 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
192 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
193 #define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
195 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
196 #define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
197 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
198 #endif /* CONFIG_ENV_IS_IN_DATAFLASH */
201 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
203 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
204 #define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */
205 #define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
206 #define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */
208 #define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
209 #define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
210 #define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */
211 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
213 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 }
215 #define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
216 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
217 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
218 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
220 #define CONFIG_SYS_HZ 1000
221 #define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
222 /* AT91C_TC_TIMER_DIV1_CLOCK */
224 #define CONFIG_STACKSIZE (32*1024) /* regular stack */
226 #ifdef CONFIG_USE_IRQ
227 #error CONFIG_USE_IRQ not supported