2 * Rick Bronson <rick@efn.org>
4 * Configuation settings for the AT91RM9200DK board.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /* ARM asynchronous clock */
29 #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
30 #define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
31 /* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
33 #define AT91_SLOW_CLOCK 32768 /* slow clock */
35 #define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
36 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
37 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
38 #define CONFIG_SETUP_MEMORY_TAGS 1
39 #define CONFIG_INITRD_TAG 1
41 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
42 #define CFG_USE_MAIN_OSCILLATOR 1
44 #define MC_PUIA_VAL 0x00000000
45 #define MC_PUP_VAL 0x00000000
46 #define MC_PUER_VAL 0x00000000
47 #define MC_ASR_VAL 0x00000000
48 #define MC_AASR_VAL 0x00000000
49 #define EBI_CFGR_VAL 0x00000000
50 #define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
53 #define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
54 #define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
55 #define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
58 #define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
59 #define PIOC_BSR_VAL 0x00000000
60 #define PIOC_PDR_VAL 0xFFFF0000
61 #define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
62 #define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
63 #define SDRAM 0x20000000 /* address of the SDRAM */
64 #define SDRAM1 0x20000080 /* address of the SDRAM */
65 #define SDRAM_VAL 0x00000000 /* value written to SDRAM */
66 #define SDRC_MR_VAL 0x00000002 /* Precharge All */
67 #define SDRC_MR_VAL1 0x00000004 /* refresh */
68 #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
69 #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
70 #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
71 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
73 * Size of malloc() pool
75 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
76 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
78 #define CONFIG_BAUDRATE 115200
80 #define CFG_AT91C_BRGR_DIVISOR 33 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
86 /* define one of these to choose the DBGU, USART0 or USART1 as console */
91 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
93 #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
95 #define CONFIG_BOOTDELAY 3
96 /* #define CONFIG_ENV_OVERWRITE 1 */
98 #define CONFIG_COMMANDS \
103 CFG_CMD_AUTOSCRIPT | \
108 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
109 #include <cmd_confdefs.h>
111 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
112 #define SECTORSIZE 512
114 #define ADDR_COLUMN 1
116 #define ADDR_COLUMN_PAGE 3
118 #define NAND_ChipID_UNKNOWN 0x00
119 #define NAND_MAX_FLOORS 1
120 #define NAND_MAX_CHIPS 1
122 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
123 #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
125 #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
126 #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
128 #define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
130 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
131 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
132 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
133 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
134 /* the following are NOP's in our implementation */
135 #define NAND_CTL_CLRALE(nandptr)
136 #define NAND_CTL_SETALE(nandptr)
137 #define NAND_CTL_CLRCLE(nandptr)
138 #define NAND_CTL_SETCLE(nandptr)
140 #define CONFIG_NR_DRAM_BANKS 1
141 #define PHYS_SDRAM 0x20000000
142 #define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
144 #define CFG_MEMTEST_START PHYS_SDRAM
145 #define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
147 #define CONFIG_DRIVER_ETHER
148 #define CONFIG_NET_RETRY_COUNT 20
149 #define CONFIG_AT91C_USE_RMII
151 #define CONFIG_HAS_DATAFLASH 1
152 #define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
153 #define CFG_MAX_DATAFLASH_BANKS 2
154 #define CFG_MAX_DATAFLASH_PAGES 16384
155 #define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
156 #define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
158 #define PHYS_FLASH_1 0x10000000
159 #define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
160 #define CFG_FLASH_BASE PHYS_FLASH_1
161 #define CFG_MAX_FLASH_BANKS 1
162 #define CFG_MAX_FLASH_SECT 256
163 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
164 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
166 #undef CFG_ENV_IS_IN_DATAFLASH
168 #ifdef CFG_ENV_IS_IN_DATAFLASH
169 #define CFG_ENV_OFFSET 0x20000
170 #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
171 #define CFG_ENV_SIZE 0x2000 /* 0x8000 */
173 #define CFG_ENV_IS_IN_FLASH 1
174 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
175 #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
176 #define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */
178 #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
179 #define CFG_ENV_SIZE 0x2000 /* 0x8000 */
180 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
181 #endif /* CFG_ENV_IS_IN_DATAFLASH */
184 #define CFG_LOAD_ADDR 0x21000000 /* default load address */
186 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
187 #define CFG_BOOT_SIZE 0x00 /* 0 KBytes */
188 #define CFG_U_BOOT_BASE PHYS_FLASH_1
189 #define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */
191 #define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */
192 #define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
193 #define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */
194 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
196 #define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
198 #define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
199 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
200 #define CFG_MAXARGS 16 /* max number of command args */
201 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
204 /*-----------------------------------------------------------------------
205 * Board specific extension for bd_info
207 * This structure is embedded in the global bd_info (bd_t) structure
208 * and can be used by the board specific code (eg board/...)
212 /* helper variable for board environment handling
214 * env_crc_valid == 0 => uninitialised
215 * env_crc_valid > 0 => environment crc in flash is valid
216 * env_crc_valid < 0 => environment crc in flash is invalid
223 #define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
224 /* AT91C_TC_TIMER_DIV1_CLOCK */
226 #define CONFIG_STACKSIZE (32*1024) /* regular stack */
228 #ifdef CONFIG_USE_IRQ
229 #error CONFIG_USE_IRQ not supported